Massachusetts Institue of TechnologyDepartment of Electrical Engineering and Computer Science6.111 - Introductory Digital Systems Laboratory (Spring 2007)Laboratory 4 Check Off SheetStudent Name:6.111 Staff Member Signature/Date:Part A: VGA InterfaceYou must show a TA the following for check off:• State transition diagram of your VGA interface • Verilog code for the VGA interface• A “screenshot” of a Pong game: a border, ball, paddle, and MIT logo Part B: Pong• State transition diagrams for your major-minor FSMs• Design methodology, design partitioning, and testing• Your Pong game working correctlyBe able to respond to any of the following questions:• What is the advantage of the major-minor FSM setup?• Explain briefly how VGA worksMassachusetts Institute of TechnologyDepartment of Electrical Engineering and Computer Science6.111 - Introductory Digital Systems Laboratory (Spring 2007)Laboratory 4 - MIT PongIssued: March 16, 2007 Part A Checkoff: recommended by March 23, 2007 Part A and B Checkoff Due: April 6, 2007 Report Due: April 9, 2007 (1PM in 38-107)1. IntroductionThe purpose of this lab is to become familiar with VGA, the display system of a typical PC. Youwill use a major-minor FSM setup to build and debug a version of the classic video game, Pong(Figure 1). As with previous labs, you will use FSMs to control the system. By the end of thelaboratory, you will be familiar with how VGA works, will be able to implement digital systemsinvolving VGA, and will understand how to construct complex systems. We will use the Major/Minor FSM concept described in lecture. 2. ProcedureThe laboratory consists of three phases. The first phase is the design phase. You should readthrough the lab and plan your design. It will be helpful to review your design with a member ofFigure 1. Screenshot of Pongthe teaching staff. In particular, it would be helpful to read the documentation of how VGA worksat the website: http://www-mtl.mit.edu/Courses/6.111/labkit/vga.shtmlThe second phase is to interface with the VGA. Your goal is to create a “screenshot” of a Ponggame, which consists of the border, the paddle, the ball, and the MIT logo in the background.The third phase will build on top of that, where you will actually implement the game. You areasked to build the logic so the paddle and ball move in a similar fashion to those in Pong. Yourdesign should be structured so that a top-level FSM controls other minor FSMs which control therest of your system. You will be required to turn in a detailed report of this laboratory.3. Task DescriptionYour first goal, Part A, is to create a still image of a Pong game in progress. You will learn howthe VGA works and how to interface to VGA (you may use problem set 3, problem 4 to code theVGA interface). Ideally, once you finish Part A, all the details of the VGA interface will beabstracted away so you can supply information for your Part B logic with little concern about thedisplay. One way to do this is to have a block that draws all of the components, and you inputlocations of the ball and paddle to that block. The only difference between Part A and Part B willbe whether you input a fixed location (still-image) or a dynamic location from Part B (game).Your ultimate goal is to create a one-player version of Pong. The user will be able to control apaddle on the left side of the screen, and use the paddle to hit and direct a ball to the wall on theright side of the screen. The ball should be able to bounce freely off of the top and bottom bor-ders, and should bounce off the wall back toward the left side, so the user may hit the ball again.Should the user miss the ball with the paddle, the ball will continue and freeze once it reaches thevery edge of the left side, signaling the game is over. Your overall system should have several user inputs:1) A reset button, which the user presses to restart the game, either in the middle of a game or when the game is over.2) up and down buttons which the user hits to control the paddle.3) A 2-bit speed switch (2-bits for x and 2-bits for y) which controls the initial speed of the ballduring gameplay. The speed sets the initial velocity of the ball in units of pixels per frame (bothin the x and y directions)4. System OrganizationA logical block diagram is shown in Figure 2. As mentioned earlier, you are to use a major-minorFSM setup, though how to partition it is up to you. Unlike previous labs, we have intentionallyleft some details undefined to give you flexibility in your design. There are certain tradeoffs suchas complexity, modularity, and system performance. Be ready to justify your partitioning in thelab report. Also note the user interface: a 2-bit switch to control the initial speed of the ball andthe necessary buttons to allow the user to move paddles.5. VGA Output and CheckoffPart A of the lab is properly displaying to the VGA. Your objective is to produce a “screenshot”of the field. The field is 640x480, the ball is an 8x8 pixel square, and the paddle is a 8x64 rectan-gle. The MIT logo should be red, the background black, and the paddle, ball, and border shouldbe white. The full pixel layout is shown in Figure 5. (For the MIT logo, you may use the MIT colors: MIT Red - R: 8'b0101_1111, G: 8'b0001_1111, B: 8'b0001_1111 andMIT Gray - R: 8'b0100_1111, G: 8'b0100_1111, B: 8'b0011_1111)The values of vga_out_red, vga_out_green, vga_out_blue (each 8 bit values) determines the colorof the pixel. Notice that for this video DAC, the number of unique colors is 28 * 28 * 28 = 224 or16 million colors. This is often referred to as 24 bit or true color. White is composed of pixelswith all ones. Black is all zeros. Debounce andControl UnitMajor FSM Minor FSM 1 Minor FSM 2 VGADisplay Fieldresetspeed_xreset_sync. . .paddle_yball_xball_ypixel_countline_countupvga signals(global)RGB signalsFigure 2. Block Diagram.Synchronizer2down DCMlabkit clock pixel clock (31.5Mhz) - to all modules(vga_out_blank_b, vga_out_sync_bvga_out_hsync, vga_out_vsync,vga_out_pixel_clock) up_syncdown_sync99101010(27Mhz)24speed_y2VGA BlockThe VGA Block is responsible for correctly sending various signals to the VGA display, such asthe horizontal and vertical blanking signals. You probably will want to implement this using afinite state machine. Additionally, you might want the block to also keep track of and producepixel counts (horizontal
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