Appendix A. Modules in Alphabetical Order `timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: 6.111 // Engineer: Mariela Buchin // Module Name: AD670 //////////////////////////////////////////////////////////////////////////////// module AD670(clock_3mhz, reset_sync, sample, status, datain, read, dataout);//, state); input clock_3mhz, reset_sync, sample, status; input [7:0] datain; //these are the actual values being spit out of the 670 chip output read; output [7:0] dataout; //this will hold the data from the 670 chip and update only during the read cycle // output [3:0] state; //only use for test module reg read; reg [7:0] LED, dataout; //Internal State reg [3:0] state; reg [3:0] nextstate; reg read_int; reg load_e; reg status_d1, status_d2; parameter IDLE = 0; parameter CONV0 = 1; parameter CONV1 = 2; parameter CONV2 = 3; parameter WAITSTATUSHIGH = 4; parameter WAITSTATUSLOW = 5; parameter READDELAY0 = 6; parameter READDELAY1 = 7; parameter READCYCLE = 8; always @ (posedge clock_3mhz ) begin if (reset_sync) begin state <= IDLE; dataout <= 8'b00000000; read <= 1; //in idle state read is high end else begin state <= nextstate; dataout <= LED; status_d1 <= status; status_d2 <= status_d1;2 read <= read_int; end end always @ (state or status_d2 or sample) begin read_int= 1; //these are default values case (state) IDLE: begin read_int = 1; if(sample) nextstate= CONV0; end CONV0:begin read_int= 0; nextstate= CONV1; end CONV1:begin read_int= 0; nextstate= CONV2; end CONV2:begin read_int= 0; nextstate= WAITSTATUSHIGH; end WAITSTATUSHIGH:begin //wait until the chip says it is done converting if (status_d2) nextstate= WAITSTATUSLOW; else nextstate= WAITSTATUSHIGH; end WAITSTATUSLOW:begin if (!status_d2) nextstate= READDELAY0; else nextstate= WAITSTATUSLOW; end READDELAY0:begin nextstate= READDELAY1; end READDELAY1:begin nextstate= READCYCLE; end READCYCLE:begin LED = datain; //the output bits only change during the read cycle nextstate= IDLE; end default: begin nextstate= IDLE; end endcase end endmodule3 `timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: Bon Voyage // Engineer: Fishy // // Create Date: 14:20:49 04/21/06 // Design Name: // Module Name: WeightFSM // Project Name: // Target Device: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module WeightFSM( weightforce); // F = m g // F = Weight Force // m = mass // g = gravitational acceleration (approx 10) output [16:0] weightforce; wire [16:0] weightforce; parameter mass = 1; parameter gravity = 10; // Scaled assign weightforce = mass * gravity; endmodule `timescale 1ns / 1ps4 //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 16:55:54 05/01/2006 // Design Name: AD670 // Module Name: AD670_Test.v // Project Name: ADConverter // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: AD670 // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module AD670_Test_v; // Inputs reg clock_3mhz; reg reset_sync; reg sample; reg status; reg [7:0] datain; // Outputs wire read; wire [7:0] LEDs; wire [3:0] state; // Instantiate the Unit Under Test (UUT) AD670 uut ( .clock_3mhz(clock_3mhz), .reset_sync(reset_sync), .sample(sample), .status(status), .datain(datain), .read(read), .LEDs(LEDs), .state(state) ); always #10 clock_3mhz = ~clock_3mhz; initial begin // Initialize Inputs5 clock_3mhz = 0; reset_sync = 1; sample = 0; status = 0; datain = 0; // Wait 100 ns for global reset to finish #50; reset_sync = 0; #50; sample = 1; #50; sample = 0; end endmodule `timescale 1ns / 1ps6 //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 13:58:43 05/17/2006 // Design Name: AD670 // Module Name: ADtester.v // Project Name: finalproject // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: AD670 // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module ADtester_v; // Inputs reg clock_3mhz; reg reset_sync; reg sample; reg status; reg [7:0] datain; // Outputs wire read; wire [7:0] dataout; wire [3:0] state; // Instantiate the Unit Under Test (UUT) AD670 uut ( .clock_3mhz(clock_3mhz), .reset_sync(reset_sync), .sample(sample), .status(status), .datain(datain), .read(read), .dataout(dataout), .state(state) ); always #10 clock_3mhz = ~clock_3mhz; initial begin7 // Initialize Inputs clock_3mhz = 0; reset_sync = 1; sample = 0; status = 0; datain = 0; #50; reset_sync = 0; #50; sample = 1; datain = 9; #50; sample = 0; #50; status = 1; #50; status = 0; #200; sample = 1; datain = 3; #50; sample = 0; #50; status = 1; #50; status = 0; end endmodule8 `timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 21:51:56 05/07/06 // Design Name: // Module Name: Alpha1 // Project Name: // Target Device: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module Alpha1(clk, pitch, alpha); input clk; input [9:0] pitch; output [7:0] alpha; wire [7:0] alpha; rom alpha_rom(pitch, clk, alpha); endmodule9 //////////////////////////////////////////////////////////////////////////////// // Company: //
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