Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 – Introductory Digital Systems Laboratory General Information In-charge and Lecturer Prof. Anantha Chandrakasan, Room 38-107, 258-7619, [email protected] Secretary Margaret Flaherty, Room 38-107, x3-0016, [email protected] TAs Kyeong-Jae Lee ([email protected], x3-7350, Rm 38-600) Theodoros Konstantakopoulos ([email protected], x3-7350, office hours in 38-600) Javier Castro ([email protected], x 3-7350, office hours in 38-600) LAs Christopher Falling ([email protected]), Amir Hirsch ([email protected]), James J. Wnorowski ([email protected]), Yun Wu ([email protected]) Technical Instructor Gim P. Hom ([email protected], Room 38-644, x4-3373) Recommended Reading (Purchase is NOT required). Logic Design: Randy Katz, Gaetano Borriello, Contemporary Logic Design, Pearson Education, 2005. Verilog: Samir Palnitkar, Verilog HDL, Pearson Education (2nd edition). (Quantum Books, located at 4 Cambridge Center, Kendall Square, Phone: (617) 494-5042, www.quantumbooks.com). 6.111 Homepage http://web.mit.edu/6.111/www/s2006/ Component Pinouts/Data Pinouts for most components easily available through the web (e.g., do a google search to locate the appropriate data sheet). We will post most of the relevant sheets needed for the labs on the course web site. Conduct of the Subject (minor changes may be made): Classes In the first couple of weeks of the term, there will be lectures on Friday (to quickly ramp up on material needed for lab 1). Then, Fridays will be used for recitations (three parallel recitation sections from 1-2pm). Lectures and recitations are discontinued at the end of the term so you can focus on the final project (see course schedule for details). We will meet in the lecture hall (34-101) for project group presentations after the block diagram conferences. Notification of particulars of the project presentations will be sent by email to [email protected] Lab (Room 38-600) The laboratory facilities are located on the sixth floor of Building 38. Each student will be issued his/her own Laboratory Kit which includes a proto-board, discrete components, a USB flash drive, oscilloscope probes, logic analyzer pods, wire stripper, chip extraction tool, etc. The FPGA kits are shared and located on the lab benches. Please turn-off the power to the kits when you are done using them. In the Digital Systems Laboratory (Room 38-600) you will find logic analyzers and oscilloscopes needed for the lab exercises. Please check the lab hours posted on the website for the hours. The lab will not be staffed by Teaching Assistants (TAs) or Lab Aides (LAs) all of the open hours. The schedule of TAs and LAs will be available on the course web page. NO FOOD or DRINKS in the lab (38-600) There are lockers for the safe storage of your kits along the 5th and 6th floor corridors of building 34. Apply at the 6th-floor instrument room desk for one. You should also remember to periodically back up all of your important files (both on Athena and the USB flash drive). When the sixth floor entrance is locked, the alarm system for the lab is usually activated. You are to enter and exit via the 5th floor. If you get stuck in the Lab after closing, you MUST have a TA let you out. Laboratory Assignments All laboratory exercises must be completed; these are intended to prepare you for the term project. In doing these exercises, each student works individually. We strongly recommend that you use a computer-based drawing package to draw block diagrams and schematics for the lab reports and final project. Problem Sets Three problem sets will be issued. The problem sets will emphasize the material covered in lectures and recitations and the primary goal is to help you prepare for the labs. Quiz There will be one quiz during the term before Drop Date. Term Project The most important assignment is the Term Project, about which you will receive more detailed instruction later. In doing this assignment, you will work with one or, at most, two partners. You should begin finding your partner(s) early in the term. Grading Policy Late work will be penalized. Lateness of the lab assignments will result in a 20% per day penalty for work completed 1-5 working days after the due date. No point credit will be given for unexcused lateness exceeding 5 days. The Lab 1 Checkoff sheet is to be initialed by a TA or LA and included with your report. Note that the checkoff sheet is NOT the report. Lab 1 report template is posted on the web site. Lab 2 report will be used for part of the CIM requirement. More details will be provided in lecture.Lab 3 will only include the checkoff. There is no need to write a detailed lab report for lab3. The lab will have instruction on what is to be turned. Lab 4 has an intermediate checkoff (not graded) and the final checkoff. There is virtually no modification required to a report depending on the working of your lab implementation. However, reports with no lab effort will receive a zero. The term project requirements must be completed in accordance with the schedule given in the instructions. You must make a presentation of your part of your project to the rest of the class after the logic diagram conference. You must demonstrate (i.e., present) your term project even if it does not fully function, and you must submit the written report in order to receive a passing grade. The following approximate weights will be used to determine your course grade: Quiz 10% Problem Sets (3) 3% 4 Lab Exercises Lab 1 (check-off, report) 9% Lab 2 (check-off, report) 10% Lab 3 (check-off, no report) 7% Lab 4 (check-off, report) 11% Writing (Lab 2 revised report - part of CIM requirement) 10% Class participation (lectures, recitations, project presentations) 3% Final Project 37% We construct a histogram of these summary numbers and proceed to discuss individual performances of all students. Some of the factors considered are: 1. Completion of labs. Past history has been that it is rare for a student to receive an A without completing the labs. 2. Project performance. a) Any student who does not turn in a final project report will receive an F. b) Students who do not construct a project will receive an F. c) Project complexity is an important factor in
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