System on a Chip Steven Hall 6.111: Introductory Digital Systems Laboratory December 14, 2005 Abstract The goal of this project was to design and implement a complete computer system, with a 64-bit processor at its core. The design encompassed a total of twelve significant modules, seven of which comprised the cpu module, which itself combined with the five others to create the computer module. For this project, all the designed modules were written in Verilog, and then the entire computer module was programmed into the FPGA labkit, which was then attached to peripheral devices (a keyboard and a monitor). Additionally, in order to facilitate the creation of code to run on this computer, the instruction set was elaborated for use by an assembler. This project served as a very in-depth experience in designing and implementing a large digital system at every level of complexity.Table of Contents Section Page Abstract 1 Table of Contents 2 Overview 3 Description 8 Microsequencer 8 Reg Manager 9 ALU Manager 9 Trap 10 Systimer 11 Interrupt Handler 11 Control 12 CPU 13 Figure 1. CPU Block Diagram 14 Memory 15 Stack 15 Timer 16 LFSR 16 I/O 17 Computer 17 Figure 2. Computer Block Diagram 18 Testing and Debugging 19 Conclusion 21 Instruction Set Reference 23 Appendix: Verilog 26 Computer 26 I/O 27 Memory 29 Stack 30 Timer 31 CPU 32 Microsequencer 36 Reg Manager 39 ALU Manager 41 Trap 47 Systimer 49 Interrupt Handler 50 Control 54Overview This project entailed the construction of a fully functional computer system on the FPGA. The key component of this design is the CPU, which is a 64-bit RISC processor designed for general purpose use, and its various submodules, including a microsequencer, two register files, two ALUs, a trap handler, a system timer, and an interrupt handler (in addition to a module containing the control logic with governs the rest of the modules). The all-encompassing computer module also contains additional modules to support the CPU, which include memory, a stack, a timer, a random number generator, and an input-output module (capable of interfacing with a keyboard and a monitor). For this project, every module mentioned was either created in Verilog or using Xilinx’s CoreGen program (since the entire design was intended to be programmed to the labkit). The following paragraphs survey each module’s purpose in the computer. First, considering the cpu module and its components, the microsequencer module is responsible for keeping track of the location in memory of the current instruction, as well as calculating the next instruction to be executed, so that the CPU can fetch the new instruction in time for execution in the next cycle. Additional responsibilities for this module involve anything that manipulates the instruction counter, including jumps, (un)conditional branches, calls, and interrupts (where these last two groups have the property that the normally next instruction counter is saved, allowing execution to return to the point after the call or interrupt). The next major submodule of the CPU is the reg_manager module, which is a thin wrapper for the two register files (regfile_word and regfile_byte). First of all, the purpose of a register file is quick and easily accessible storage (two properties which main memory does not have) of temporary variables (in the case of this CPU, there are 256 word-size and 32 byte-sizeregisters). Perhaps more important, however, is the fact that this is the first glimpse of the two separate datapaths in this processor, one being word-sized and the other byte-sized. The only real interaction between these two datapaths occurs in this module, through operations which can split a word into eight bytes or join eight bytes together to form a word. Following the flow of data through the processor, the next module is the alu_manager, which is once again a thin wrapper for two modules, alu_word and alu_byte. These two ALUs operate independently of each other, and are capable of performing addition, subtraction, shifting (arithmetic and logical), rotation, the standard Boolean operations (and, or, xor, nand, nor, xnor), and three unique bitwise functions (unary reverse, and binary concatenation and interleaving). Generally, the result of ALU computation will be written back to the register file, except in special cases. Operating at the same level in the dataflow, but in a separate branch, is the trap module. This special purpose module is responsible for performing some operations which should be in the normal datapath, but would unduly increase the minimum period of the processor (additionally, these operations would not be expected to be used as frequently anyway). The actual execution of these operations involves pipelining the logic to reduce the minimum clock period and disabling the microsequencer during computation to allow the operation to finish before the next instruction is processed. The original design included word-size and byte-size versions of both multipliers and dividers (which simultaneously performed the modulus operation), but the dividers were removed from the final design. The systimer module is a very special purpose module which also happens to be part of a small branch of the word datapath, although its true function has very little relation to the computation discussed previously. This module generates a system timer interrupt at a certaininterval of microseconds, which can be set by the user (the default is one million, or one second). This ability would mainly be used by code requiring the timing of specific intervals or code using that periodic event to keep time for some other reason (games often fall into these categories). The penultimate submodule of the CPU is the interrupt_handler, which is responsible for managing all the interrupts generated by the computer. These interrupts are generally intended to be used to signal an exceptional condition (i.e. division by zero or ALU overflow), but they are often employed as a means of signaling between the CPU and external devices or the user himself (through a special operation for generating interrupts). The majority of this module’s task is controlling which interrupts have
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