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MIT 6 111 - Four-Channel FPGA Ambisonic Audio System

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Four-Channel FPGA Ambisonic Audio SystemBen Bloomberg !! 6.111 Fall 2009Bloomberg DesignsTable of ContentsIntroduction! 1Overview! 1Ambisonic Audio Processing! 1System Description! 2Audio Subsystem Modules! 2USB Reader! 2DLP-USB245M! 2Design Iterations ! 2Coefficient ROMS! 4Coeff_full Module! 4Generating Coefficients! 5Encoder! 5Summing! 5Decoder! 6Design Considerations! 6Audio Output Driver! 6DCM Manipulation! 6Bloomberg DesignsFour-Channel FPGA Ambisonic Audio System! iPCM1681 Clocks! 6Serial Audio Output! 7PCM1681 Control! 7Video Subsystem Modules! 7XGA! 7Ambisonic UI! 7Preset Manager! 8Sync Coord Module! 8Conclusion! 9Design & Testing! 9DLP-USB245M FIFO Interface! 9PCM-1681 Interface! 10Audio DSP Logic! 11User Interface! 12System Integration! 12Final Thoughts! 12References! 13Appendix A: Verilog Implementation! 14Appendix B: Verilog Test Fixtures! 15Appendix B: Python Implementation! 16Bloomberg DesignsFour-Channel FPGA Ambisonic Audio System! iiIntroductionOverviewThe goal of ambisonics is to create a representation of 3-dimensional audio in a format that can be used on a speaker system of any size and shape. This document describes an efficient FPGA solution for encoding and decoding 3rd order ambisonic audio. To facilitate testing, there is an audio input module based on a DLP-USB254M FIFO chip and a multichannel audio output module based on a Texas Instruments Burr-Brown PCM-1681 8-channel digital to analog converter. This allows four channels of audio to be placed in real time and output across as many as 8 speakers. The system also contains 4 preset locations which can be edited, saved and recalled. When switching between presets, the system interpolates the location coordinates of each channel so that audio does not stutter or jump, but fades smoothly. As channels move further away from the center of the of the sound field, their gain decreases by a constant factor, so that they seem to disappear into the distance.The system is controlled via a push buttons and switches on the labkit device, and user feedback is accomplished using XGA output to show the location of the each incoming channel on the screen.The computer interface to send audio to the system is a simple python script relying on FTDI native D2XX drivers and the PyUSB library for those drivers.Ambisonic Audio ProcessingAmbisonic encoding and decoding is based on spherical harmonics. Virtual audio sources are encoded by taking their location in space and describing it as a linear combination of a basis set of orthogonal spherical harmonics. When separated, the terms of the linear combination can be used as elements of a vector representation of the source. An ‘encoded ambisonic stream’ consists of one mono channel of audio and 15 copies of that channel, scaled by the relative components of each harmonic for that channel’s location in space. This means that the decoding process is essentially a linear algebra projection onto another vector which represents the location of a physical source (a loudspeaker). Encoded 16 channel streams may be added together to encapsulate multiple virtual sources in a single 16 channel representation. This representation can be decoded for any position in space, creating an accurate reproduction of each virtual source for a specific physical source location. The result is dynamic panning that adapts to any configuration of output devices.Additionally, because the encoders and decoders operate independently, the process is completely parallel and thus, perfect for FPGA acceleration.Bloomberg DesignsFour-Channel Ambisonic Audio System! 1System DescriptionAudio Subsystem ModulesThe audio subsystem is responsible for getting audio samples from the computer, encoding them ambisonically, summing each of the encoded streams together, and then decoding the stream for each physical source. The audio system works using a push-pull method, where a pulse from the audio output driver clears the data in every DSP module. At that point the first module, the coeff_rom, generates coefficients based on the current coordinates from the user interface. When complete, it asserts a coeffs_valid signal to the encoders, which in turn assert encoder_valid to the summing device. The summing device asserts a summing_valid signal to each of the decoders and on the next audio pulse, if the decoders have asserted their decoder_valid signals, the audio is pushed to output driver, the DSP is again cleared and the process starts over. USB ReaderThe USB reader module uses a FIFO buffer to grab individual bytes from a DLP-USB245M chip. It is a state-machine architecture that uses 8 states to pull each byte from the buffer. Unlike the DSP, it pushes a new sample of audio to each of the encoders on every audio pulse.DLP-USB245MThe DLP devices USB FIFO allows the computer to send data at fairly high rates using a externally buffered transmission bus. On the labkit, the data is made available 1 byte at a time using a signaling scheme that allows bytes to be pulled at any clock speed. When new data is available, the chip sets an output pin RXF low. At that point the FPGA sets the RD pin low to retrieve the data. Once RD goes high again, the DLP chip prepares the next byte in the fifo and sets RXF low when it is ready. In the final USB reader module, the RD bit is set to the inverse of the MSB of the state, so that RD is low for the first four states and high for the last four states. During 3rd state, data is stored to a FIFO on the labkit. In order to ensure the correct timing, the fifo_wr bit is registered and set 2 cycles before the RD pin goes high. The fifo_wr bit is checked on the next cycle and data is latched to the FIFO on the following cycle.Design IterationsThe USB Reader state-machine went through several design iterations. Initially, the audio data was not streaming quickly enough to the lab kit. This was diagnosed using the second_notify module to illuminate one of the labkit LEDs when the buffer filled or emptied. A timing diagram for an early version of the USB state-machine is pictured below in figure 1. This diagram was captured when RD was calculated as a separate register, causing 1 cycle of delay on the RD line. Bloomberg DesignsFour-Channel Ambisonic Audio System! 2Figure 1: USB state machine using 8 states and a delayed RD signalAfter much time spent trying to optimize the state-machine, it was realized that there were 6ms long delays in the USB data and that the chip and the


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MIT 6 111 - Four-Channel FPGA Ambisonic Audio System

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