6.111 Fall 2005 Lecture 1, Slide 1Welcome to 6.111!Introductory Digital Systems LaboratoryHandouts:Info form (yellow)Course CalendarLecture slidesLectures:Ike ChuangChris TermanTAs:Javier CastroEric FellheimerJae LeeWillie Sanchez6.111 Fall 2005 Lecture 1, Slide 2Course Website (http://mit.edu/6.111)6.111 Fall 2005 Lecture 1, Slide 36.111 Goals• Fundamentals of logic design– combinational and sequential blocks• System integration with multiple components– FPGAs, memories, discrete components, etc.• Learn a Hardware Description Language (Verilog)• Interfacing issues with analog components– ADC, DAC, sensors, etc. • Understand different design methodologies• Understand different design metrics– component/gate count and implementation area, switching speed, energy dissipation and power• Design & implement a substantial digital system• Have fun!6.111 Fall 2005 Lecture 1, Slide 4Labs: learning the ropes• Lab 1– Experiment with gates, design & implement some logic– Learn about lab equipment in the Digital Lab (38-600): oscilloscopes and logic analyzers– Introduction to Verilog• Lab 2– Design and implement a Finite State Machine (FSM)– Use Verilog to program an FPGA– Report and its revision will be evaluated for CI-M• Lab 3– Design a complicated system with multiple FSMs(Major/Minor FSM)– Voice recorder using AC97 codec and SRAMs• Lab 4– Video circuits: a simple Pong game6.111 Fall 2005 Lecture 1, Slide 5Final Project• Done in groups of two (or sometimes three) • Open ended• You and the staff negotiate a project proposal– Must emphasize digital concepts, but inclusion of analog interfaces (e.g., data converters, sensors or motors) common and often desirable– Proposal Conference, several Design Reviews• Design presentation in class (% of the final grade for the in-class presentation)• Staff will provide help with project definition and scope, design, debugging, and testing• It is extremely difficult for a student to receive an A without completing the final project6.111 Fall 2005 Lecture 1, Slide 6Evaluation• Midterm (11/2): 20%• Labs: 30%– Labs 1 & 2: 5%, Labs 3 & 4: 10%• CI-M paper: 10%• Final Project: 40%– Deadlines and participation: 5% – Quality and organization of presentation and report: 5% – Complexity, innovation and risk: 10% – Problem definition: 2% – Architecture: 3% – Design (modularity, Verilog): 5% – Functionality: 10% • A large number of students do "A" level work and are, indeed, rewarded with a grade of "A". The corollary to this is that, since average performance levels are so high, punting any part of the subject can lead to a disappointing grade.6.111 Fall 2005 Lecture 1, Slide 7Why Digital? A Thought ExperimentHTTHGoal: transmit results of 100 coin flips6.111 Fall 2005 Lecture 1, Slide 8Experiment #1: Analog EncodingHTTH100 coin flips → 2100possibilitiesTransmit voltage N/2100for possibility #NRequired voltage resolution = 1/2100 = ~8e-31 voltsimpossible to reliably transmit/receive voltages with that resolution6.111 Fall 2005 Lecture 1, Slide 9Rethink basic system architecture• Noise and inaccuracy are inevitable; we can’t reliably transmit/receive/manipulate “infinite”information-- we must design our system to tolerate some amount of error if it is to process information reliably.• A system is a structure that is guaranteed to exhibit a specified behavior, assuming all of its components obey their specified behaviors.How is this achieved? CONTRACTS!Every system component will have clear obligations and responsibilities. If contracts are violated all bets are off.6.111 Fall 2005 Lecture 1, Slide 10Going Digital• Digital representation = information encoded as a sequence of symbols chosen from a (small) set.• Keep in mind that the world is not digital, we will simply engineer it to behave that way. Furthermore, we must use real physical (analog, continuous) phenomena to implement digital designs!• Common choices– Binary symbols (0, 1)– If we have DC connectivity (wired):encode using voltages/currents– If we don’t have DC connectivity (wireless):encode using frequency/phase• Going digital keeps the contracts simple – limit quantum of information we process in exchange for reliablityWe’ll workwith these6.111 Fall 2005 Lecture 1, Slide 11Using Voltages Digitally• Key idea: don’t allow “0” to be mistaken for a “1”or vice versa• Use the same “uniform representation convention”for everycomponent and wire in our digital system• To implement devices with high reliability, we outlaw “close calls” via a representation convention which forbids a range of voltages between “0” and “1”.voltsValid“0”Valid“1”Forbidden ZoneInvalidConsequence: notion of valid and invalid signals6.111 Fall 2005 Lecture 1, Slide 12A Digital Processing ElementStaticdisciplineOutput a “1” if at least 2 out of 3 ofmy inputs are a “1”.Otherwise, output “0”.I will generate a validoutput in no more than2 minutes after seeing valid inputsinput Ainput Binput Coutput Y• A combinational deviceis a circuit element that has– one or more digitalinputs– one or more digital outputs– a functional specificationthat details the value of each output for every possible combination of valid input values– a timing specificationconsisting (at minimum) of an upper bound tpdon the required time for the device to compute the specified output values from an arbitrary set of stable, valid input values6.111 Fall 2005 Lecture 1, Slide 13Why have processing blocks?• The goal of modular design:ABSTRACTION• What does that mean anyway:– Rules simple enough for a 6-3 to follow…– Understanding BEHAVIOR without knowing IMPLEMENTATION– Predictable composition of functions– Tinker-toy assembly– Guaranteed behavior under REAL WORLD circumstances6.111 Fall 2005 Lecture 1, Slide 14A Combinational Digital System• A set of interconnected elements is a combinational deviceif– each circuit element is a combinational device– every input is connected to exactly one output or a constant (eg, some vast supply of 0’s and 1’s)– the circuit contains no directed cycles• Why is this true?– Given an acyclic circuit meeting the above constraints, we can derive functional and timing specs for the input/output behavior from the specs of its components!– We’ll see lots of examples soon. But first, we need to build some combinational
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