6.111 Lecture # 4 Ss Counting is a very important function in the digital world, and it is donein a variety of waysHere is a 'ripple' counter using negative edge triggered T flip flopsCount Sequence:The LSB is on the left in this diagram. It alwaystoggles.The transition of 1 -> 0 of each 'bit' triggers a toggle of the next most significant bit 0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 0Here is why it is called a 'ripple' counter:The effect of each input transition must affect all bits, and it does this by rippling through from LSB to MSBAn odd effect is that the transient count is always less than the truecount.Can COUNT fast, but maybe can't be READ fast!'Synchronous' counters use more logic to reduce the time to stable outputs.Here is a simplified version of the 4 bit 74LS163 counterNote that, while all bits of the synchrous counter are set very close to thesame time, they may not be set at exactlythe same time.This means that there is a rapidly changing transient state of the counter.If it passes through all one's it will cause a 'glitch' on the ripple carry out. You are asked to look for this in Lab 1, but you may not see it!The '163 will 'count' ONLY if P and T are both high Note that RCO is the AND of all four bits and T.So if this is input to the T input of the next higher nibble, it indicates that all bits below are set, so the next higher nibbleshould count.P is 'count enable', and P and T should be tied together ONLYfor the least significant 4 bits of a counter.With a little ingenuity, you can achieve all kinds of count sequences. Theseare both divide by twelve circuits.Finite State machinesWe have already seen simple FSM's in Flip Flops and CountersBut you can do much more complex things with them After a clock edge, the 'machine' assumes a state that depends on where it was before the edge and its inputs just before the edgeIf the input is wired to the output logic, the output canchange asynchronously in response to changes in theinput.On the other hand, if theinput is used ONLY in thenext-state logic, the outputis fixed during each clockcycle and only changesafter the clock edge.We have automated procedures to build the logic foe finite state machines, buthere is an example of a very simple machine.This is one way of describing anFSM, in terms of transitions on each clock edge.4 possible states require 2 bits ofstate. This is a mealey machineIt is straightforward to build a truth table for 'next state' based on 'presentstate' and input. The output is also derived from the same variables.Here is the logic that would be required to implement that FSM, if it were made out of discrete gates.Programmable Logic: Here are two old PALsNote I, O and I/O pinsPower and Ground are consistently upper right and lower leftClock is pin 1 and /OE is lower right, if those are requiredThese are historic parts: fast, cheap and you probably won't ever see oneHere is a schematicdiagram for the 16L8: wecan learn more about thisby considering its parts.It more complex parts it isnot usual to see the wholewiring diagram as you do here.Programmable Array Logic (PAL)The basic element is the 'product term': essentially a wired AND of input signalsand their complementsYou can make things like a*b*/cAll of these devices synthesize a large OR of ANDsOr the output can be registered, as in the 16R4Note that in this case the 'feedback' is from the register, not the pin.Pin 1 is now dedicated to being theclock input and is not available as aregular input. Pin 13 (or the lower right hand pin) is output enable and is not available as a regular inputProgrammable Logic Devices have become more complexHere is the block diagram level diagram of the 22v10The Programmable Array is familiarNote the ORs employ different numbers of product termsAnd here the output architecture is also programmableThis is the output logic macrocell for the 22V10Output enable is derived froma single product termOutput Select has 4 choices:Direct or invertedRegistered direct or inverted'Feedback' input is either from the register or from the pin The clock is still from Pin 1 The select bits are programmedCPLD's are just more complicated PLD'sHere is a diagram for the Cypress '374i partHere is a program logic blockNote there are both I/O and 'buried' macrocellsInput/Output Macrocell (programmable architecture)Not a lot different from the PALNote there are four available clock lines: chosen by a MUXLab Kits have four '374i partsNote that interconnections limit flexibility of signal
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