A Labkit Listingmodule labkit (beep, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch,ac97_bit_clock,vga_out_red, vga_out_green, vga_out_blue, vga_out_sync_b,vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync,vga_out_vsync,tv_out_ycrcb, tv_out_reset_b, tv_out_clock, tv_out_i2c_clock,tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b,tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset,tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1,tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff,tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read,tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock,ram0_data, ram0_address, ram0_adv_ld, ram0_clk, ram0_cen_b,ram0_ce_b, ram0_oe_b, ram0_we_b, ram0_bwe_b,ram1_data, ram1_address, ram1_adv_ld, ram1_clk, ram1_cen_b,ram1_ce_b, ram1_oe_b, ram1_we_b, ram1_bwe_b,clock_feedback_out, clock_feedback_in,flash_data, flash_address, flash_ce_b, flash_oe_b, flash_we_b,flash_reset_b, flash_sts, flash_byte_b,rs232_txd, rs232_rxd, rs232_rts, rs232_cts,mouse_clock, mouse_data, keyboard_clock, keyboard_data,clock_27mhz, clock1, clock2,disp_blank, disp_data_out, disp_clock, disp_rs, disp_ce_b,disp_reset_b, disp_data_in,button0, button1, button2, button3, button_enter, button_right,button_left, button_down, button_up,switch,led,user1, user2, user3, user4,18daughtercard,systemace_data, systemace_address, systemace_ce_b,systemace_we_b, systemace_oe_b, systemace_irq, systemace_mpbrdy,analyzer1_data, analyzer1_clock,analyzer2_data, analyzer2_clock,analyzer3_data, analyzer3_clock,analyzer4_data, analyzer4_clock);output beep, audio_reset_b, ac97_synch, ac97_sdata_out;input ac97_bit_clock, ac97_sdata_in;output [7:0] vga_out_red, vga_out_green, vga_out_blue;output vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock,vga_out_hsync, vga_out_vsync;output [9:0] tv_out_ycrcb;output tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data,tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b,tv_out_subcar_reset;input [19:0] tv_in_ycrcb;input tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef,tv_in_hff, tv_in_aff;output tv_in_i2c_clock, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso,tv_in_reset_b, tv_in_clock;inout tv_in_i2c_data;inout [35:0] ram0_data;output [18:0] ram0_address;output ram0_adv_ld, ram0_clk, ram0_cen_b, ram0_ce_b, ram0_oe_b, ram0_we_b;output [3:0] ram0_bwe_b;inout [35:0] ram1_data;output [18:0] ram1_address;output ram1_adv_ld, ram1_clk, ram1_cen_b, ram1_ce_b, ram1_oe_b, ram1_we_b;output [3:0] ram1_bwe_b;input clock_feedback_in;output clock_feedback_out;inout [15:0] flash_data;19output [23:0] flash_address;output flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_byte_b;input flash_sts;output rs232_txd, rs232_rts;input rs232_rxd, rs232_cts;input mouse_clock, mouse_data, keyboard_clock, keyboard_data;input clock_27mhz, clock1, clock2;output disp_blank, disp_clock, disp_rs, disp_ce_b, disp_reset_b;input disp_data_in;output disp_data_out;input button0, button1, button2, button3, button_enter, button_right,button_left, button_down, button_up;input [7:0] switch;output [7:0] led;inout [31:0] user1, user2, user3, user4;inout [43:0] daughtercard;inout [15:0] systemace_data;output [6:0] systemace_address;output systemace_ce_b, systemace_we_b, systemace_oe_b;input systemace_irq, systemace_mpbrdy;output [15:0] analyzer1_data, analyzer2_data, analyzer3_data,analyzer4_data;output analyzer1_clock, analyzer2_clock, analyzer3_clock, analyzer4_clock;//////////////////////////////////////////////////////////////////////////////// I/O Assignments//////////////////////////////////////////////////////////////////////////////// Audio Input and Outputassign beep= 1’b0;assign audio_reset_b = 1’b0;assign ac97_synch = 1’b0;assign ac97_sdata_out = 1’b0;20// Video Outputassign tv_out_ycrcb = 10’h0;assign tv_out_reset_b = 1’b0;assign tv_out_clock = 1’b0;assign tv_out_i2c_clock = 1’b0;assign tv_out_i2c_data = 1’b0;assign tv_out_pal_ntsc = 1’b0;assign tv_out_hsync_b = 1’b1;assign tv_out_vsync_b = 1’b1;assign tv_out_blank_b = 1’b1;assign tv_out_subcar_reset = 1’b0;// Video Input//assign tv_in_i2c_clock = 1’b0;assign tv_in_fifo_read = 1’b1;assign tv_in_fifo_clock = 1’b0;assign tv_in_iso = 1’b1;//assign tv_in_reset_b = 1’b0;assign tv_in_clock = clock_27mhz;//1’b0;//assign tv_in_i2c_data = 1’bZ;// tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2,// tv_in_aef, tv_in_hff, and tv_in_aff are inputs// SRAMsassign ram0_data = 36’hZ;assign ram0_address = 19’h0;assign ram0_adv_ld = 1’b0;assign ram0_clk = 1’b0;assign ram0_cen_b = 1’b1;assign ram0_ce_b = 1’b1;assign ram0_oe_b = 1’b1;assign ram0_we_b = 1’b1;assign ram0_bwe_b = 4’hF;assign ram1_data = 36’hZ;assign ram1_address = 19’h0;assign ram1_adv_ld = 1’b0;assign ram1_clk = 1’b0;assign ram1_cen_b = 1’b1;assign ram1_ce_b = 1’b1;assign ram1_oe_b = 1’b1;assign ram1_we_b = 1’b1;assign ram1_bwe_b = 4’hF;assign clock_feedback_out = 1’b0;// Flash ROM21assign flash_data = 16’hZ;assign flash_address = 24’h0;assign flash_ce_b = 1’b1;assign flash_oe_b = 1’b1;assign flash_we_b = 1’b1;assign flash_reset_b = 1’b0;assign flash_byte_b = 1’b1;// RS-232 Interfaceassign rs232_txd = 1’b1;assign rs232_rts = 1’b1;// LED Displays//assign disp_blank = 1’b1;//assign disp_clock = 1’b0;//assign disp_rs = 1’b0;//assign disp_ce_b = 1’b1;//assign disp_reset_b = 1’b0;//assign disp_data_out = 1’b0;// Buttons, Switches, and Individual LEDsassign led = 8’hFF;// User I/Osassign user1 = 32’hZ;assign user2 = 32’hZ;assign user3 = 32’hZ;assign user4 = 32’hZ;// Daughtercard Connectorsassign daughtercard = 44’hZ;// SystemACE Microprocessor Portassign systemace_data = 16’hZ;assign systemace_address = 7’h0;assign systemace_ce_b = 1’b1;assign systemace_we_b = 1’b1;assign systemace_oe_b = 1’b1;// Logic Analyzer//assign analyzer1_data = 16’h0;assign analyzer1_clock = 1’b1;//assign analyzer2_data = 16’h0;//assign analyzer2_clock = clock_64mhz;//assign analyzer3_data = 16’h0;22assign analyzer3_clock = 1’b1;//assign analyzer4_data = 16’h0;assign analyzer4_clock = 1’b1;///////////////////////////////////////////////////////////////////////// Fingerprint ID///////////////////////////////////////////////////////////////////////// use FPGA’s digital clock manager to produce a// 31.5 MHz pixel clock from clock_27mhz // 15, 14wire clock_32mhz_unbuf,clock_32mhz;DCM pxl_clk_dcm (.CLKIN(clock_27mhz),
View Full Document
Unlocking...