L7: Memory Basics and TimingMemory Classification & MetricsMemory Array ArchitectureLatch and Register Based MemoryStatic RAM (SRAM) Cell (The 6-T Cell)Interacting with a Memory DeviceMCM6264C 8k x 8 Static RAMReading an Asynchronous SRAMAddress Controlled ReadsWriting to Asynchronous SRAMSample Memory Interface LogicMulti-Cycle Read/Write (less aggressive, recommended timing)Simulation from Previous SlideVerilog for Simple Multi-Cycle AccessVerilog for Simple Multi-Cycle AccessTesting MemoriesAn ApproachA Simple Memory TesterSynchronous SRAM MemoriesZBT Eliminates the Wait StatePipelining Allows Faster CLKEPROM Cell – The Floating Gate TransistorInteracting with Flash and (E)EPROMDynamic RAM (DRAM) CellAsynchronous DRAM OperationAddressing with Memory MapsKey Messages on Memory DevicesYou Should Understand Why…L7: 6.111 Spring 20071Introductory Digital Systems LaboratoryL7: Memory Basics and Timing L7: Memory Basics and Timing Acknowledgements: ¾Nathan Ickes, Rex Min, Yun Wu¾ Lecture material adapted from J. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits: A Design Perspective” Copyright 2003 Prentice Hall/Pearson.L7: 6.111 Spring 20072Introductory Digital Systems LaboratoryMemory Classification & MetricsMemory Classification & MetricsRead-Write MemoryNon-VolatileRead-WriteMemoryRead-Only Memory (ROM)EPROME2PROMFLASHRandomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedFIFOLIFOKey Design Metrics:1. Memory Density (number of bits/µm2) and Size2. Access Time (time to read or write) and Throughput 3. Power DissipationL7: 6.111 Spring 20073Introductory Digital Systems LaboratoryMemory Array ArchitectureMemory Array ArchitectureInput-Output(M bits)2L-KBit LineWord LineStorage CellM.2KAmplify swing torail-to-rail amplitudeSelects appropriate word(i.e., multiplexor)Sense Amps/DriverColumn DecodeAK-1A0Row Decode2L-Krow byMx2Kcolumn cell arrayAKAK+1AL-1L7: 6.111 Spring 20074Introductory Digital Systems LaboratoryLatch and Register Based MemoryLatch and Register Based MemoryPositive LatchNegative LatchRegister Memory10DQCLK01DQCLKDGQ DGQClkDNegative latchQQMPositive latch Works fine for small memory blocks (e.g., small register files) Inefficient in area for large memories – density is the key metric in large memory circuitsHow do we minimize cell size?L7: 6.111 Spring 20075Introductory Digital Systems LaboratoryStatic RAM (SRAM) Cell (The 6Static RAM (SRAM) Cell (The 6--T Cell)T Cell)WLBLVDDM5M6M4M1M2M3BLQQWLBLBLWLQ QWrite: set BL and BL to 0 and VDDor VDDand 0 and then enable WL (i.e., set to VDD)Read: Charge BL and BL to VDDand then enable WL (i.e., set to VDD). Sense a small change in BL or BL State held by cross-coupled inverters (M1-M4) Static Memory - retains state as long as power supply turned on Feedback must be overdriven to write into the memoryL7: 6.111 Spring 20076Introductory Digital Systems LaboratoryInteracting with a Memory DeviceInteracting with a Memory DeviceTri-state DriverMemory Matrix…… Address pins drive row and column decoders Data pins are bidirectional and shared by reads and writes Output Enable gates the chip’s tristate driver Write Enable sets the memory’s read/write mode Chip Enable/Chip Select acts as a “master switch”Data PinsReadLogicWriteLogicRow DecoderAddress PinsSense Amps/DriversColumn DecoderWrite enableChip EnableOutput EnableinoutenableIf enable=0out = ZIf enable =1out = inWrite enableL7: 6.111 Spring 20077Introductory Digital Systems LaboratoryMCM6264C 8k x 8 Static RAMMCM6264C 8k x 8 Static RAMDQ[7:0]Memory matrix256 rows32 ColumnRow DecoderColumn DecoderSense Amps/Drivers……A2A3A4A5A7A8A9A11A0A1A6A10A12E1E2WGMCM6264CAddressDataDQ[7:0]138Chip Enables E1E2Write Enable WOutput Enable GOn the outside:On the inside:Pinout Same (bidirectional) data bus used for reading and writing Chip Enables (E1 and E2) E1 must be low and E2 must be high to enable the chip Write Enable (W) When low (and chip is enabled), the values on the data bus are written to the location selected by the address bus Output Enable (G) When low (and chip is enabled with W=0), the data bus is driven with the value of the selected memory locationL7: 6.111 Spring 20078Introductory Digital Systems LaboratoryReading an Asynchronous SRAMReading an Asynchronous SRAMBus tristate timeAddressE1GData Read cycle begins when all enable signals (E1, E2, G) are active Data is valid after read access time Access time is indicated by full part number: MCM6264CP-12 Æ12ns Data bus is tristated shortly after G or E1 goes highAddress ValidData ValidAccess time (from address valid)Access time (from enable low)Bus enable time(Tristate)E2 assumed high (enabled), W =1 (read mode)L7: 6.111 Spring 20079Introductory Digital Systems LaboratoryAddress Controlled ReadsAddress Controlled ReadsBus tristate timeAccess time (from address valid)Bus enable timeAddressE1GDataAddress 3Address 2Address 1Data 2Data 3Data 1Contamination timeE2 assumed high (enabled), W =1 (read mode) Can perform multiple reads without disabling chip Data bus follows address bus, after some delayL7: 6.111 Spring 200710Introductory Digital Systems LaboratoryWriting to Asynchronous SRAMWriting to Asynchronous SRAMAddressE1WData Data latched when W or E1 goes high (or E2 goes low) Data must be stable at this time Address must be stable before W goes low Write waveforms are more important than read waveforms Glitches to address can cause writes to random addresses!Address ValidAddress setup timeWrite pulse widthData setup timeE2 and G are held highData ValidData hold timeAddress hold timeL7: 6.111 Spring 200711Introductory Digital Systems LaboratorySample Memory Interface LogicSample Memory Interface LogicClock/E1GWAddressDataData for writeAddress for write Address for readData readWrite occurs here, when E1 goes highData can be latched hereFSMClockDQAddressRead dataWrite dataControl(write, read, reset) Drive data bus only when clock is low Ensures address are stable for writes Prevents bus contention Minimum clock period is twice memory access timeWrite cycle Read cycleData[7:0]Address[12:0]WGE1SRAME2ext_chip_enableext_write_enableext_output_enableext_addressext_dataVCCQDQDint_dataFPGAL7: 6.111 Spring 200712Introductory Digital Systems LaboratoryMultiMulti--Cycle Read/Write Cycle Read/Write (less aggressive, recommended timing)(less aggressive, recommended timing)write states 1-3write completes
View Full Document
Unlocking...