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MIT 6 111 - Logic Analyzers, Digital Oscilloscope, and PALs

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1. Read and understand the whole assignment.2. Design, build, test, debug, and fix each exercise in turn. Be sure to answer all the questions in the report template before ...Figure 1 : (a) Logic Level Measurement (Measure voltage at OUT node). (b) Power Supply Wiring.Figure 2 : Timing Characteristics (10%, 50%, 90% marked).Figure 3 : Ring Oscillator (using a 74LS04).Figure 4 : Glitch Measurement Circuit (74LS00).Figure 5 : Clock and Ripple Counter.Figure 6 : Synchronous Counter WiringFigure 7 : Hex digits on the seven-segment display1Massachusetts Institute of TechnologyDepartment of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory (Fall 2004)Laboratory 1 - Logic Analyzers, Digital Oscilloscope, and PALsIssued: September 8, 2004Checkoff and Report Due: September 24, 2004IntroductionThis lab assignment introduces you to important tools and devices that we will be using through-out the term. You will be introduced to the following:• HP 1662AS, a multichannel logic analyzer with an integrated two-channel digital scope. • 74LS TTL series chips, including the ‘00, ‘04, ‘163, ‘393, ‘74• 74HC00, a CMOS NAND gate• 1.8432 MHz Crystal Oscillator• Warp 6.3 for Windows (for Verilog programming)• PAL programmers to program a 22V10 Programmable Array Logic (PAL)• TTL and CMOS voltage levels• Karnaugh Maps and Boolean Algebra• Simple Verilog• Latches and Flip-flops, Simple Sequential and asynchronous circuits• 7-segment DisplayThe following are relevant handouts that you should be using in conjunction with this lab:• Lectures 1-5• Safety Memo• How to use the Logic Analyzer/OscilloscopeProcedureThis lab is divided into several exercises to guide you through the design, construction, anddebugging process. You will be asked to wire circuits for many of the exercises. Save all of thesecircuits until you have completed the lab as many of these circuits might be reused in subsequentparts of this lab.1. Read and understand the whole assignment.2. Design, build, test, debug, and fix each exercise in turn. Be sure to answer all the questions in the report template before you get checked off. You do NOT have to get checked-off on a exercise before proceeding to the next one. For each exercise, be sure to have the appropriate figures ready. Turn in the completed report template to your TA after your checkoff.2Exercise 1: TTL/CMOS Static Electrical CharacteristicsThe logic values of 1 and 0 are represented by voltage levels in the hardware logic implementa-tion. The voltage levels and other electrical characteristics are not standardized from one logicfamily to another. 6.111 will use both TTL (Transistor-Transistor Logic) and CMOS (Comple-mentary Metal-Oxide Semiconductor) logic. The voltage ranges for the two logic families are notcompatible.In this exercise, you will first measure the electrical characteristics of a TTL and CMOS gateusing the circuit in Figure 1. Wire up this circuit using a 74LS00 part. Do not forget to wire powerand ground! These connections are usually omitted from logic diagrams, as the power and groundof the 74LS series are generally the top-right and bottom-left pin, respectively. Typically, the topof the chip has a small semi-circular cutout, or a white dot next to pin 1.Ground the input of the inverter (the first NAND) and measure the output voltage using the oscil-loscope. Be sure to be using the voltage markers on the oscilloscope.Connect the input to a logic ‘1’ and repeat the measurement.Next, use a 74HC00 and wire up the same circuit and hook VCC to a +5V supply. Perform thesame measurements and record your results.Look up the valid input and output voltage ranges using the datasheet for a 74LS00 and a74HC00. For each experiment, do your output values satisfy the range specified in the datasheets? Consider interfacing a TTL inverter to a CMOS inverter and vice versa. Look at the datasheettitled “HCMOS Family Characteristics”. Based on the +5V supply you used, find out the recom-mended input voltage for HCMOS inputs. Discuss potential issues when interfacing TTL andCMOS components? Run the two experiments (interface TTL to CMOS and vice versa) and makevoltage measurements. OUTIN12374LS0017814+5Gnd+5Figure 1: (a) Logic Level Measurement (Measure voltage at OUT node). (b) Power Supply Wiring.3Exercise 2: Build Your Own Ring OscillatorImportant timing parameters associated with the speed of digital logic gates are the propagationdelay time tPD, and the output signal rise and fall times, tR and tF. Propagation delay is a measureof how much time is required for a signal to change state. It is measured as the time from the50% point of the input to the 50% point of the output (Figure 2). It is often cited as the average ofthe high-to-low and low-to-high delays (corresponding to the two transitions). The rise and falltimes represent the amount of time for a signal to change state. To measure rise and fall times, youshould be using the 10% to the 90% point, or vice versa. Construct the ring oscillator shown in Figure 3 using a 74LS04 with as little wire as possible.From this circuit, determine the average propagation delay of a TTL inverter by measuring theperiod of oscillation by using the time markers on the oscilloscope. You can determine this bydetermining the number of gates a signal must travel through to complete a full period of oscilla-tion.What should the period of oscillation be with 3 inverters in the ring? Rewire the circuit and mea-sure the period. Comment on the new result.Insert a long piece of wire (about 3 feet) into the ring of 3 inverters. Observe how this extra lengthof circuit affects the signal. Can you explain the change?Finally, take a single inverter, and wire the output to the input. The voltage should be stable. If itisn’t, connect a capacitor (0.01 µF) between this single node and ground to stabilize the voltage.Measure the voltage, and explain the significance of this voltage.InOuttPDtfalltriseFigure 2: Timing Characteristics (10%, 50%, 90% marked).12345613121110Figure 3: Ring Oscillator (using a 74LS04).4Exercise 3: GlitchesWire up the circuit in Figure 4 using a 1.8432 MHz crystal oscillator and a 74LS00. Be sure towire the crystal oscillator right side up. Pin 1 should be marked with a dot. The output GLIT is apurposely glitchy output caused by the circuit. Using the oscilloscope, measure the width of theglitch. Next, add CLK and GLIT as signals to


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