The J Computer Advay Mengle 6.111 Spring 2007 Final Project T.A: Amir Hirsch May 17, 2007 ABSTRACT This paper presents the J Computer, a processor that natively implements a subset of the Java Virtual Machine specification for Java ME CLDC v1.0a in hardware. The computer contains a 32-bit microprocessor, method code cache, and a number of hardware device modules, such as a tone generator, a PS/2 keyboard, and an alpha-blending VGA graphics renderer into which Java code running on the main processor can make remote procedure calls. The user may download arbitrary class files to the J Computer via an RS-232 connection. The design was verified in simulation, and synthesized on a Xilinx Virtex2 FPGA. Successful execution of Java implementations of a prime number discovery algorithm and a simple pong game with audio demonstrated the computer's functionality.Table of Contents I Introduction................................................................................................................................................ 2 1 Problem Statement................................................................................................................................. 2 2 Background and Motivation.................................................................................................................. 3 3 User Interaction ..................................................................................................................................... 4 4 System Architecture............................................................................................................................... 4 II Implementation.......................................................................................................................................... 4 1 Class Memory Manager......................................................................................................................... 4 2 RS-232 UART ........................................................................................................................................ 5 3 Metadata Manager.................................................................................................................................. 5 4 Bytecode Reader and Method Cache ................................................................................................... 6 5 SOP Processor ....................................................................................................................................... 6 a Instruction Set Architecture....................................................................................................................6 b Stack Manager .......................................................................................................................................6 c Control Signals ......................................................................................................................................7 6 Bytecode-to-SOP Translator................................................................................................................. 7 7 RPC Bus and Other Hardware Modules.............................................................................................. 8 III Testing and Debugging.......................................................................................................................... 9 1 Unit Testing............................................................................................................................................ 9 2 System Testing and Demonstration..................................................................................................... 9 3 Resolved and Remaining Issues............................................................................................................ 9 IV Conclusions ............................................................................................................................................ 9 1 Results..................................................................................................................................................... 9 2 Future Work......................................................................................................................................... 10 3 Acknowledgements.............................................................................................................................. 10 V References................................................................................................................................................. 10 I Introduction We give below a detailed problem statement, background and motivation, an overview of how a user interacts with the J Computer, and the high-level system architecture and specification. 1 Problem Statement The J Computer will natively execute a subset of the Java ME CLDC v1.0a bytecode in hardware. The main processor shall convert Java bytecode into a custom microcode, called simple operations (SOPs), developed for this specific purpose and thus optimized for the nature of Java instructions, and execute this microcode. The processor shall support a kernel (written in Java bytecode), the ability to execute multiple static methods, the ability to manipulate static fields, and perform 32-bit computation. The J Computer must be able to download Java class files (that have been preprocessed for formatting reasons, if necessary) via an RS-232 connection with a PC, and execute the downloaded code on the fly. The main processor must be able to connect to other modules in such a way that permits Java code to transparently perform remote procedure calls (RPC1) into these other hardware modules without knowledge of the internals of these modules. All functionality shall 1 The phrase "remote procedure call" is used here as an appeal to familiarity, but does not resemble true RPC as in full Java.be demonstrated by developing a prime number-finding program, and a simple pong game in which Java code controls the image displayed on the VGA. The design must be realized on a 6-million gate Xilinx Virtex2 XC2V6000 FPGA with limited BRAM. 2 Background and Motivation Java is a popular high-level, object-oriented language developed by Sun Microsystems, Inc., specified in [2], often used for application and web programming. One of the strengths of Java is its attempt to be
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