6.111 Fall 2005 - 1 of 6 - Midterm Exam M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 6.111 Introductory Digital Systems Laboratory Fall 2005 Midterm Exam: November 2, 2005 Name Score (out of 100) Problem 1. (25 Points) Congratulations, you’re now a consultant for Hot Logic, Inc., a startup interested in building combinational logic devices that (of course) obey the static discipline. Their chief engineer has given you the following schematic and voltage-transfer curve for their prototype inverter design, the HL-INV: 5 4 3 2 1 VOUT5 4 3 2 1 VIN A. (10 Points) Choose values for VOL, VIL, VIH and VOH so that the prototype device obeys the static discipline and has positive, non-zero noise margins. Give your values below or briefly explain why no such values can be found. Briefly explain why values can’t be found or specify voltage levels: VOL __________ VIL __________ VIH __________ VOH __________ Noise margins __________6.111 Fall 2005 - 2 of 6 - Midterm Exam B. (5 Points) Add the appropriate n-channel mosfets to the schematic below to implement a two-input HL-NAND gate with inputs IN1 and IN2 that computes 21 ININ • . C. (5 Points) Assume that all mosfets in Hot Logic’s gates have the same width and length. If we want the VOL for the HL-NAND gate to be the same as the VOL for the HL-INV gate, what value should we choose for RPU? Value for RPU (in ohms): __________________ D. (5 Points) Briefly compare the static power dissipation and noise margins of Hot Logic gates with CMOS gates.6.111 Fall 2005 - 3 of 6 - Midterm Exam Problem 2. (60 Points) The diagram below shows the schematic for an electronic lock with a combination consisting of some sequence of 0’s and 1’s. The user enters the combination by pressing the ZERO and ONE buttons in the correct sequence. If the last N digits that have been entered match the N-digit combination, the UNLOCK signal is asserted and the lock opens. You can assume that the button0 and button1 signals have been properly debounced and synchronized with CLK. A. (10 Points) The L2P module is a level-to-pulse converter that asserts its output high for 1 clock cycle after a 0-to-1 transition on its input, as shown in the timing diagram below. Complete the following Verilog implementation for the L2P module: module L2P(clk,in,out); input clk; input in; output out; endmodule L2P L2P D Q CLK Logic zeroones1,s0NEXT_STATE[1:0] BUTTON1 BUTTON0 UNLOCK NEXT_STATE[1:0]unlocknext_s1,next_s0STATE[1:0] CLK IN OUT6.111 Fall 2005 - 4 of 6 - Midterm Exam Here’s the truth table for the lock’s Logic module: s1 s0 one zero unlock next_s1 next_s0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 1 1 1 0 1 0 1 0 0 0 1 1 0 1 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 1 B. (10 Points) What’s the N-digit combination for the lock, i.e., what sequence of 0’s and 1’s will leave you with UNLOCK asserted regardless of what state the FSM was in when you started to enter the combination? Hint: use the truth table to draw a state transition diagram. You can use the back of the quiz pages as scratch paper. Lock combination: ____________________ C. (5 Points) Briefly describe what happens if both buttons are pressed simultaneously. D. (8 Points) Here are the timing parameters for the two D-Registers used to hold the current state: tCD = 0ns, tPD = 2ns, tSETUP = 2ns, tHOLD = 1ns. What are the constraints on tCD and tPD of the Logic module if we want the circuit to operate reliably with a 100MHz clock? Constraints on Logic module’s tCD: __________________ Constraints on Logic module’s tPD: __________________ E. (6 Points) For this question assume the register timing specifications given in part (D) and that the timing specifications of the Logic module are tCD = 1ns and tPD = 5ns. Complete the timing diagram below carefully indicating when STATE[0] and NEXT_STATE[0] are valid and when they are invalid. Each vertical grid line represents 1ns. STATE[0] NEXT_STATE[0] CLK6.111 Fall 2005 - 5 of 6 - Midterm Exam F. (6 Points) If the Logic module is implemented using a ROM, what size ROM would we need? Number of locations in ROM: __________________ Number of bits/location in ROM: __________________ G. (10 Points) Give a minimized sum-of-products expression for next_s[1] output of the Logic module. Hint: the Karnaugh Map template given below may be useful. Minimized sum-products expression for next_s[1]: ______________________________ 00 01 11 10 00 01 11 10 H. (5 Points) Draw a schematic diagram for a circuit that implements next_s[1]. Your circuit should using only inverters, 2-input NAND gates and 2-input NOR gates.6.111 Fall 2005 - 6 of 6 - Midterm Exam Problem 3. (15 Points) The following Verilog test jig, initially sets a to 1, b to 0 and clk to 0, waits 10 time units, sets clk to 1, waits another 10 time units and the prints out the values of a, b and c. module testjig(); reg clk,a,b; wire c; assign c = ~a; // CODE SNIPPETS ARE INSERTED HERE initial begin a = 1; b = 0; clk = 0; #10 // wait 10 time units clk = 1; #10 // wait 10 time units $display(“a=%d b=%d c=%d\n”,a,b,c); $stop; end endmodule A series of tests is run, each using one of the code snippets below substituted into the testjig module at the indicated location. For each snippet indicate the values printed out for a, b and c. Write ??? for a value if it cannot be determined using standard Verilog semantics. A. always @ (posedge clk) begin a = b; b = c; end Values: a = __________, b = __________, c = __________ B. always @ (posedge clk) begin a <= b; b <= c; end Values: a = __________, b = __________, c = __________ C. always @ (posedge clk) a = b; always @ (posedge clk) b = c; Values: a = __________, b = __________, c = __________ D. always @ (posedge clk) a <= b; always @ (posedge clk) b <= c; Values: a = __________, b = __________, c = __________ E. always @ (posedge clk) begin a <= b; b = c; end Values: a = __________, b = __________, c =
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