Sequential Logic • Digital state: the D-Register • Timing constraints for D-Registers • Specifying registers in Verilog • Blocking and nonblocking assignments • Verilog execution semantics: concurrency & nondeterminism • Examples 6.111 Fall 2008 1 Lecture 4 Reminder: Lab #2 due Thursday!Something We Can’t Build (Yet) What if you were given the following design specification: When the button is pushed: 1) Turn on the light if it is off 2) Turn off the light if it is on The light should change state within a second of the button press button light What makes this circuit so different from those we’ve discussed before? 1. “State” – i.e. the circuit has memory 2. The output was changed by a input “event” (pushing a button) rather than an input “value” 6.111 Fall 2008 2 Lecture 4Digital State One model of what we’d like to build Plan: Build a Sequential Circuit with stored digital STATE – • Memory stores CURRENT state, produced at output • Combinational Logic computes • NEXT state (from input, current state) • OUTPUT bit (from input, current state) • State changes on LOAD control input Combinational Logic Current State New State Input Output Memory Device LOAD When Output depends on input and current state, circuit is called a Mealy machine. If Output depends only on the current state, circuit is called a Moore machine. 6.111 Fall 2008 3 Lecture 4Our next building block: the D register D CLK Q The edge-triggered D register: on the rising edge of CLK, the value of D is saved in the register and then shortly afterwards appears on Q. 6.111 Fall 2008 4 Lecture 4D-Register Timing - I CLK D Q ≤tPD tPD: maximum propagation delay, CLK →Q tCD: minimum contamination delay, CLK →Q ≥tCD ≥tSETUP tSETUP: setup time How long D must be stable before the rising edge of CLK ≥tHOLD tHOLD: hold time How long D must be stable after the rising edge of CLK 6.111 Fall 2008 5 Lecture 4D-Register Timing - II CLK tPD,reg1 logic D Q D Q CLK reg1 reg2 tPD,logic tPD,reg1 + tPD,logic + tSETUP,reg2 ≤ tCLK tCLK ≥ tSETUP,reg2 The good news: you can choose tCLK so that this constraint is satisfied! tCD,reg1 tCD,logic tCD,reg1 + tCD,logic ≥ tHOLD,reg2 The bad news: you have to change your design if this constraint isn’t met. 6.111 Fall 2008 6 Lecture 4Single-clock Synchronous Circuits Single-clock Synchronous Discipline • No combinational cycles • Only care about value of combinational circuits just before rising edge of clock • Clock period greater than every combinational delay • Change saved state after noise-inducing logic transitions have stopped! We’ll use Registers in a highly constrained way to build digital systems: • Single clock signal shared among all clocked devices (one clock domain) Does that symbol register? 6.111 Fall 2008 7 Lecture 4D-Register Timing With Skew CLKreg1 logic D Q D Q CLK reg1 reg2 tPD,reg1+ tPD,logic ≥ tSETUP,reg2 tCD,reg1+tCD,logic ±skew CLKreg2 In the real world the clock signal arrives at different registers at different times. The difference in arrival times (pos or neg) is called the clock skew tskew. We can update our two timing constraints to reflect the worst-case skew: tPD,reg1+tPD,logic+ tSETUP,reg2 ≤ tCLK– tskew tCD,reg1+tCD,logic ≥ tHOLD,reg2+ tskew Thus clock skew increases the minimum cycle time of our design and makes it harder to meet register hold times. ≥ tHOLD,reg2 6.111 Fall 2008 8 Lecture 4 CLKreg2 rising edge might fall anywhere in this region.Sequential Circuit Timing Questions: • Constraints on tCD for the logic? • Minimum clock period? • Setup, Hold times for Inputs? Combinational Logic Current State New State Input Output Clock tCD,L = ? tPD,L = 5ns tCD,R = 1ns tPD,R = 3ns tS,R = 2ns tH,R = 2ns > 1 ns > 10 ns (tPD,R+tPD,L+ tSETUP,R) tSETUP,Input = tPD,L +tSETUP,R tHOLD,Input = tHOLD,R -tCD,L This is a simple Finite State Machine … more on next time! 6.111 Fall 2008 9 Lecture 4The Sequential always Block Edge-triggered circuits are described using a sequential always block module comb(input a, b, sel, output reg out); always @(*) begin if (sel) out = a; else out = b; end endmodule module seq(input a, b, sel, clk, output reg out); always @(posedge clk) begin if (sel) out <= a; else out <= b; end endmodule Combinational Sequential 6.111 Fall 2008 10 Lecture 4Note: The following is incorrect syntax: always @(clear or negedge clock) If one signal in the sensitivity list uses posedge/negedge, then all signals must. Assign any signal or variable from only one always block. Be wary of race conditions: always blocks with same trigger execute concurrently… Importance of the Sensitivity List • The use of posedge and negedge makes an always block sequential (edge-triggered) • Unlike a combinational always block, the sensitivity list does determine behavior for synthesis! module dff_sync_clear( input d, clearb, clock, output reg q ); always @(posedge clock) begin if (!clearb) q <= 1'b0; else q <= d; end endmodule D-Register with synchronous clear D-Register with asynchronous clear always block entered only at each positive clock edge always block entered immediately when (active-low) clearb is asserted module dff_sync_clear( input d, clearb, clock, output reg q ); always @(negedge clearb or posedge clock) begin if (!clearb) q <= 1'b0; else q <= d; end endmodule 6.111 Fall 2008 11 Lecture 4Blocking vs. Nonblocking Assignments • Verilog supports two types of assignments within always blocks, with subtly different behaviors. • Blocking assignment (=): evaluation and assignment are immediate always @(*) begin x = a | b; // 1. evaluate a|b, assign result to x y = a ^ b ^ c; // 2. evaluate a^b^c, assign result to y z = b & ~c; // 3. evaluate b&(~c), assign result to z end Nonblocking assignment (<=): all assignments deferred to end of simulation time step after all right-hand sides have been evaluated (even those in other active always blocks) Sometimes, as above, both produce the same result. Sometimes, not! always @(*) begin x <= a | b; // 1. evaluate a|b, but defer assignment to x y <= a ^ b ^ c; // 2. evaluate a^b^c, but defer assignment to y z <= b & ~c; // 3. evaluate b&(~c), but defer assignment to z // 4. end of time step: assign new values to x, y and z end 6.111 Fall 2008 12 Lecture 4Assignment Styles
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