6.111 Fall 2006 Lecture 7, Slide 16.111 Lecture 7Today:Demo!(or die): An Electronic Lock1.Design FSM2.Implement in Verilog3.Compile: Xilinx tool-chain4.Program labkit6.111 Fall 2006 Lecture 7, Slide 2Demo!GOAL:Build an electronic combination lock with a reset button, two number buttons (0 and 1), and an unlock output. The combination should be 01011.“0”“1”RESETUNLOCKSTEPS:1.Design lock FSM (block diagram, state transitions)2.Write Verilog module(s) for FSM3.Use Xilinx ISE7.1 (synthesis, simulation)4.Program FGPA, give it a whirl!6.111 Fall 2006 Lecture 7, Slide 3Step 1A: Block Diagramfsm_clockresetb0_inb1_inlockbuttonbuttonbuttonClockgeneratorButtonEnterButton0Button1fsmstateunlockresetb0b1LEDDISPLAYUnlockLED6.111 Fall 2006 Lecture 7, Slide 4Step 1B: State transition diagramRESETUnlock = 0“0”Unlock = 0“01”Unlock = 0“01011”Unlock = 1“0101”Unlock = 0“010”Unlock = 0010111010010RESET6 states → 3 bits6 states → 3 bits6.111 Fall 2006 Lecture 7, Slide 5Step 2: Write Verilogmodule lock(clk,reset_in,b0_in,b1_in,out);input clk,reset,b0_in,b1_in;output out;// synchronize push buttons, convert to pulses// implement state transition diagramreg [2:0] state;always @ (posedge clk)beginstate <= ???;end// generate outputassign out = ???;// debugging?endmodule6.111 Fall 2006 Lecture 7, Slide 6Step 2A: Synchronize buttons// button -- push button synchronizer and level-to-pulse converter// OUT goes high for one cycle of CLK whenever IN makes a// low-to-high transition.module button(clk,in,out);input clk;input in;output out;reg r1,r2,r3;always @ (posedge clk)beginr1 <= in; // first reg in synchronizerr2 <= r1; // second reg in synchronizer, output is in sync!r3 <= r2; // remembers previous state of buttonend// rising edge = old value is 0, new value is 1assign out = ~r3 & r2; endmoduleDQDQDQinr3r1 r2clkoutsynchronizer state6.111 Fall 2006 Lecture 7, Slide 7Step 2B: state transition diagramparameter S_RESET = 0; // state assignmentsparameter S_0 = 1;parameter S_01 = 2;parameter S_010 = 3;parameter S_0101 = 4;parameter S_01011 = 5;reg [2:0] state; always @ (posedge clk)begin // implement state transition diagramif (reset) state <= S_RESET;else case (state)S_RESET: state <= b0 ? S_0 : b1 ? S_RESET : state;S_0: state <= b0 ? S_0 : b1 ? S_01 : state;S_01: state <= b0 ? S_010 : b1 ? S_RESET : state;S_010: state <= b0 ? S_0 : b1 ? S_0101 : state;S_0101: state <= b0 ? S_010 : b1 ? S_01011 : state;S_01011: state <= b0 ? S_0 : b1 ? S_RESET : state;default: state <= S_RESET; // handle unused statesendcaseendRESETUnlock = 0“0”Unlock = 0“01”Unlock = 0“01011”Unlock = 1“0101”Unlock = 0“010”Unlock = 0010111010010RESET6.111 Fall 2006 Lecture 7, Slide 8Step 2C: generate output// it’s a Moore machine! Output only depends on current stateassign out = (state == S_01011);Step 2D: debugging?// hmmm. What would be useful to know? Current state?assign hex_display = {1'b0,state[2:0]};6.111 Fall 2006 Lecture 7, Slide 9Step 2: final Verilog implementationmodule lock(clk,reset_in,b0_in,b1_in,out, hex_display);input clk,reset,b0_in,b1_in;output out; output[3:0] hex_display;wire reset, b0, b1; // synchronize push buttons, convert to pulsesbutton b_reset(clk,reset_in,reset);button b_0(clk,b0_in,b0);button b_1(clk,b1_in,b1);parameter S_RESET = 0; parameter S_0 = 1; // state assignmentsparameter S_01 = 2; parameter S_010 = 3;parameter S_0101 = 4; parameter S_01011 = 5;reg [2:0] state; always @ (posedge clk)begin // implement state transition diagramif (reset) state <= S_RESET;else case (state)S_RESET: state <= b0 ? S_0 : b1 ? S_RESET : state;S_0: state <= b0 ? S_0 : b1 ? S_01 : state;S_01: state <= b0 ? S_010 : b1 ? S_RESET : state;S_010: state <= b0 ? S_0 : b1 ? S_0101 : state;S_0101: state <= b0 ? S_010 : b1 ? S_01011 : state;S_01011: state <= b0 ? S_0 : b1 ? S_RESET : state;default: state <= S_RESET; // handle unused statesendcaseassign out = (state == S_01011); // assign output: Moore machineassign hex_display = {1'b0,state}; // debugging endmodule6.111 Fall 2006 Lecture 7, Slide 10Programming(parallel cable)*.bitImplementation(map, place, route)rtlStep 3: Synthesis & Simulation• We will be using the Xilinx toolchain• Software: ISE 7.1i (windows / linux)Design Entry(Verilog)Synthesis(xst)Simulation(modelsim)*.v6.111 Fall 2006 Lecture 7, Slide 11Step 3A: Load source file lock.v6.111 Fall 2006 Lecture 7, Slide 12Step 3B: Compile/Synthesize6.111 Fall 2006 Lecture 7, Slide 13Step 3B: Create testbench6.111 Fall 2006 Lecture 7, Slide 14Step 3B: Create testbench6.111 Fall 2006 Lecture 7, Slide 15Step 3B: Generate Simulation Results6.111 Fall 2006 Lecture 7, Slide 16Step 4: Implementation – Program FPGA• fsm_demo.v (modified copy of labkit.v): peripherals definitions• Optimization: Placing and RoutingSynthesis(xst)Implementation(map, place, route)Programming(parallel cable)rtl*.bit• Pin assignments: User constraints filefsm_demo.v, lock.v, debounce.v, display_1hex.vlabkit.ucf6.111 Fall 2006 Lecture 7, Slide 17Step 4: Implementation – Program FPGA• Pin assignments: User constraints filelabkit.ucf6.111 Fall 2006 Lecture 7, Slide 18Clocks27 MHz2 user inputsMemory4Mx36 ZBT SRAM128 mbit Flash ROMAudioLM4550 AC’97Stereo In/OutHeadphone/micVideo InputADV7185NTSC decoderDisplay16 char5x7 dotsVGA VideoAD7125Tripple-out DAC1024 x 768 RGBVideo OutputAD7194NTSC encoderGeneral I/O9 buttons8 switches8 LED’sps/2 kbd & mouseRS-232 serialuser, LA signalsThe 6.111 Labkit: SubsystemsXilinx Virtex-II FPGAXC2V6000-6BF9576M gates1M RAM684 I/O pads0.15μm 8 layer CMOSNathan Ickes6.111 Fall 2006 Lecture 7, Slide 19Step 4A: FPGA Device AssignmentVirtex 2: xc2v6000 Package: bf957Speed: -46.111 Fall 2006 Lecture 7, Slide 20Step 4B: Add labkit files6.111 Fall 2006 Lecture 7, Slide 21Step 4C: ImplementDouble-click hereto implement design,and create the labkit.bitfileRight-click implement, select properties,Select “allow unmatched LOC constraints”6.111 Fall 2006 Lecture 7, Slide 22Step 4C: Implement• Useful reports: Resource Utilization, Timing, RTL diagram6.111 Fall 2006 Lecture 7, Slide 23Step 4C: Implement• Useful reports: Resource Utilization, Timing, RTL diagram6.111 Fall 2006 Lecture 7, Slide 24Step 4C: Implement• Useful reports: Resource Utilization, Timing, RTL diagram6.111 Fall 2006 Lecture 7, Slide 25Step 4C: Implement• Useful reports: Floorplan6.111 Fall 2006 Lecture 7,
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