L13: 6.111 Spring 2005 1Introductory Digital Systems LaboratoryL13: Final Project KickoffL13: Final Project KickoffL13: 6.111 Spring 2005 2Introductory Digital Systems LaboratoryScheduleSchedule Project Abstract (Due April 4thin class) Start discussing project ideas with the 6.111 staff Abstract should be about 1 page (clearly state the work partition) – a polished abstract will be published on the course website once your project has been finalized. Work in teams of two or three. A single person project requires special approval by the 6.111 staff. Proposal Conference with TAs (April 6-8). Bring your proposal with you. Block diagram conferences with TAs (April 11-15) Review the major components in the system and your overall design approach Each group in discussion with TA, creates a deliverables checklist (i.e., what we can expect to be demonstrated) – (Due April 20st in class). Specify the device components you need to acquire (small budget allocated for each project if component does not exist in the stock room). Get approval from the 6.111 staff and your TA will contact John Sweeney to obtain the parts. Project Design Presentation (in 34-101) on April 20, 22, 25, 27 Each group will make an electronic presentation (power point or PDF) Everyone is required to attend all days (not just the days you are presenting) – this will count in your participation grade. Each student will write comments (anonymous) which will be provided to the presenting group as feedback. Final project check-off (with teaching staff) on May 10: 30 minutes Final project presentations and video taping on May 11: ~3-4 minutes (videos to be posted on the course website with permission) Final project report (in electronic format, which will be published with permission on the course website) due May 12 by 5PM (no late project check-offs or reports accepted) See project information handout for 6.905 additional units signupL13: 6.111 Spring 2005 3Introductory Digital Systems LaboratoryChoosing A TopicChoosing A Topic You only have 5 weeks total (once your proposal abstract is turned in) to do this project. Be realistic in what you take on.It is important to complete your project.It is very difficult to receive an “A” in the class without completing the final project. The complexity should be equal or larger than lab3 for each student. Quite often you will need to include analog building blocks (video, wireless, motors, etc.). However, keep in mind that this is a digital class and your design should demonstrate digital design principles. Complexity and innovation factor. We will give credit to innovative applications, design approaches More complex is not necessarily betterL13: 6.111 Spring 2005 4Introductory Digital Systems LaboratoryGrading (35 points Total)Grading (35 points Total) Report and Presentation (5 points) Problem Definition and Relevance, Architecture, Design methodology (7 points) What is the problem and why is it important System architecture and partitioning Design choices and principles used Style of coding All of the above should be stated in the project presentation and report Functionality (16 points) Did you complete what your promised (i.e., graded by your customized checklist) Innovation (7 points)L13: 6.111 Spring 2005 5Introductory Digital Systems LaboratoryDesign RulesDesign Rules Use hierarchical design Partition your design into small subsystems that are easier to design and test Design each sub-system so they can be tested individually When appropriate, use Major/Minor FSMs Use the same clock edge for all edge-triggered flip-flops Beware of clock skew Avoid problems from ‘glitches’ Always assume that combinational logic glitches Never clock a register from the output of combinational logic Never drive a critical control signal such as write enable from the output of combinational logic Ensure a stable combinational output before it is sampled by CLK. Create glitch-free signals byz Registering outputs z Gating the clockL13: 6.111 Spring 2005 6Introductory Digital Systems LaboratoryDesign Rules Design Rules --22 Avoid tristate bus contention by design Synchronize all asynchronous signals Use two back to back registers Use memory properly Avoid address changes when WE is true Make sure your write pulse is glitch free Power supply can be noisy Use bypass capacitors to filter noise Chip-to-chip communication Beware of noise (inductance) Might need to synchronize signals Can also use “asynchronous” protocolsL13: 6.111 Spring 2005 7Introductory Digital Systems LaboratoryHow to Make Your Project WorkHow to Make Your Project Work(see handout)(see handout) Read all of the handout It is ‘old’ but all of it is good advice Sections that are particularly relevant are: Wiring Errors Care and Feeding of the Power Supply Unused Inputs Behavior of Ungrounded Parts Tri-State Logic Signals Handling CMOS Parts Wire Routing Clock Distribution Gating the Clock RAM Write Pulses Synchronizer Errors Testing Strategies Driving High Current DevicesDocument Courtesy of Tom Knight and Don TroxelL13: 6.111 Spring 2005 8Introductory Digital Systems LaboratoryNew New LabkitLabkit Based on a huge Xilinx FPGA (need to learn new tools) Built-in audio/video interfaces, high-speed memory Supports moderately high-speed designs (50-100MHz)FPGA I/O (128 signals)Composite and S-Video in/outVGA outputPS/2 mouse, keyboardAlphanumeric DisplayAudio line in/outRS-2326M gate FPGA4MB ZBT SRAM16MB flash ROMHeadphones/microphoneDesigned by Nathan Ickes (MIT) in collaboration with Xilinx Designed by Nathan Ickes (MIT) in collaboration with
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