L5: 6.111 Spring 2004 1Introductory Digital Systems LaboratoryL5: Simple Sequential Circuits and L5: Simple Sequential Circuits and VerilogVerilogAcknowledgements: Nathan Ickes and Rex MinL5: 6.111 Spring 2004 2Introductory Digital Systems LaboratoryKey Points from L4 (Sequential Blocks)Key Points from L4 (Sequential Blocks)Classification: Latch: level sensitive (positive latch passes input to output on high phase, hold value on low phase) Register: edge-triggered (positive register samples input on rising edge) Flip-Flop: any element that has two stable states. Quite often Flip-flop also used denote an (edge-triggered) registerDClkQQDDClkQQDPositiveLatchPositiveRegister Latches are used to build Registers (using the Master-Slave Configuration), but are almost NEVER used by itself in a standard digital design flow. Quite often, latches are inserted in the design by mistake (e.g., an error in your Verilog code). Make sure you understand the difference between the two. Several types of memory elements (SR, JK, T, D). We will most commonly use the D-Register, though you should understand how the different types are built and their functionality.L5: 6.111 Spring 2004 3Introductory Digital Systems LaboratoryKey Points from L4 : System TimingKey Points from L4 : System TimingDClkQInCombinationalLogicDClkQCLKTsuThTsuThTcqTcq,cdTcqTcq,cdFF1INCLoutCLoutTl,cdTsuTlogicT > Tcq+ Tlogic+ TsuTcq,cd+ Tlogic,cd> TholdL5: 6.111 Spring 2004 4Introductory Digital Systems LaboratoryThe Sequential The Sequential alwaysalwaysBlockBlock Edge-triggered circuits are described using a sequential always blockmodule combinational(a, b, sel,out);input a, b;input sel;output out;reg out;always @ (a or b or sel) beginif (sel) out = a;else out = b;end endmodulemodule sequential(a, b, sel, clk, out);input a, b;input sel, clk;output out;reg out;always @ (posedge clk) beginif (sel) out <= a;else out <= b;end endmoduleCombinational Sequential10seloutab10seloutabDQclkL5: 6.111 Spring 2004 5Introductory Digital Systems LaboratoryNote: The following is incorrect syntax: always @ (clear or negedge clock)If one signal in the sensitivity list uses posedge/negedge, then all signals must. Assign any signal or variable from only one always block, Be wary of race conditions: always blocks execute in parallelImportance of the Sensitivity ListImportance of the Sensitivity List The use of posedge and negedge makes an always block sequential (edge-triggered) Unlike a combinational always block, the sensitivity list doesdetermine behavior for synthesis! module dff_sync_clear(d, clearb, clock, q);input d, clearb, clock;output q;reg q;always @ (posedge clock) beginif (!clearb) q <= 1'b0;else q <= d; endendmoduleD Flip-flop with synchronous clear D Flip-flop with asynchronous clearmodule dff_async_clear(d, clearb, clock, q);input d, clearb, clock;output q;reg q;always @ (negedge clearb or posedge clock) beginif (!clearb) q <= 1’b0;else q <= d;endendmodulealways block entered only at each positive clock edgealways block entered immediately when (active-low) clearb is assertedL5: 6.111 Spring 2004 6Introductory Digital Systems LaboratorySimulationSimulationtc-qClear on Clock Edge DFF with Synchronous ClearClear happens on falling edge of clearb DFF with Asynchronous ClearL5: 6.111 Spring 2004 7Introductory Digital Systems Laboratory1. Evaluate a | b but defer assignment of x2. Evaluate a^b^c but defer assignment of y3. Evaluate b&(~c) but defer assignment of z1. Evaluate a | b, assign result to x2. Evaluate a^b^c, assign result to y3. Evaluate b&(~c), assign result to zBlocking vs. Blocking vs. NonblockingNonblockingAssignmentsAssignments Verilog supports two types of assignments within always blocks, with subtly different behaviors. Blocking assignment: evaluation and assignment are immediate Nonblocking assignment: all assignments deferred until all right-hand sides have been evaluated (end of simulation timestep) Sometimes, as above, both produce the same result. Sometimes, not!always @ (a or b or c)beginx = a | b;y = a ^ b ^ c;z = b & ~c;endalways @ (a or b or c)beginx <= a | b;y <= a ^ b ^ c;z <= b & ~c;end4. Assign x, y, and z with their new valuesL5: 6.111 Spring 2004 8Introductory Digital Systems LaboratoryAssignment Styles for Sequential LogicAssignment Styles for Sequential Logic Will nonblocking and blocking assignments both produce the desired result?module nonblocking(in, clk, out);input in, clk;output out;reg q1, q2, out;always @ (posedge clk) beginq1 <= in;q2 <= q1;out <= q2;end endmoduleDQDQDQin outq1 q2clkFlip-Flop Based Digital Delay Linemodule blocking(in, clk, out);input in, clk;output out;reg q1, q2, out;always @ (posedge clk) beginq1 = in;q2 = q1;out = q2;end endmoduleL5: 6.111 Spring 2004 9Introductory Digital Systems LaboratoryUse Use NonblockingNonblockingfor Sequential Logicfor Sequential Logicalways @ (posedge clk) beginq1 <= in;q2 <= q1;out <= q2;endalways @ (posedge clk) beginq1 = in;q2 = q1;out = q2;end DQDQDQin outq1 q2clkDQinoutclk“At each rising clock edge, q1, q2, and outsimultaneously receive the old values of in, q1, and q2.”“At each rising clock edge, q1 = in. After that, q2 = q1 = in. After that, out = q2 = q1 = in. Therefore out = in.” Blocking assignments do not reflect the intrinsic behavior of multi-stage sequential logicGuideline: use nonblocking assignments for sequential always blocksq1 q2L5: 6.111 Spring 2004 10Introductory Digital Systems LaboratorySimulationSimulationNon-blocking SimulationBlocking SimulationL5: 6.111 Spring 2004 11Introductory Digital Systems LaboratoryUse Blocking for Combinational LogicUse Blocking for Combinational Logic Nonblocking and blocking assignments will synthesize correctly. Will both styles simulate correctly? Nonblocking assignments do not reflect the intrinsic behavior of multi-stage combinational logic While nonblocking assignments can be hacked to simulate correctly (expand the sensitivity list), it’s not elegant Guideline: use blocking assignments for combinational always blocksx <= a & b;Assignment completion(Given) Initial Conditiona changes; always block triggereda b c x y Deferred1 1 0 1 10 1 0 1 10 1 0 1 1 x<=00 1 0 1 1 x<=0, y<=10 1 0 01y <= x | c;Nonblocking Behaviorx = a & b;(Given) Initial Conditiona changes; always block triggeredy = x | c;Blocking Behaviora b c x y1 1 0 1 10 1 0 1 10 1 0 0 10 1 0 0 0module
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