6.111 Fall 2007 Lecture 7, Slide 1Design Example: Level-to-Pulse• A level-to-pulse converter produces a single-cycle pulse each time its input goes high.• It’s a synchronous rising-edge detector.• Sample uses:– Buttons and switches pressed by humans forarbitrary periods of time– Single-cycle enable signals for countersLevel toPulseConverterL PCLKWhenever input L goesfrom low to high......output P produces asingle pulse, one clockperiod wide.6.111 Fall 2007 Lecture 7, Slide 2High input,Waiting for fall11P = 0L=1L=000Low input, Waiting for riseP = 001Edge Detected!P = 1L=1L=0L=0L=1• State transition diagram is a useful FSM representation and design aid:Step 1: State Transition Diagram• Block diagram of desired system:D QLevel toPulseFSML Punsynchronizeduser inputSynchronizerEdge DetectorThis is the output that results fromthis state. (Moore or Mealy?)P = 011Binary values of statesL=0“if L=0 at the clock edge,then stay in state 00.”L=1“if L=1 at the clock edge,then jump to state 01.”D QCLK6.111 Fall 2007 Lecture 7, Slide 3Step 2: Logic Derivation00Low input, Waiting for riseP = 001Edge Detected!P = 111High input,Waiting for fallP = 0L=1L=1L=0L=0L=1L=0101010LIn001100POut101010S0+101000S1+110000S1NextStateCurrent State111100S0• Combinational logic may be derived using Karnaugh mapsX1101X000010110100X1111X000010110100S1S0LS1S0Lfor S1+:for S0+:011X0010S1for P:S0Comb.LogicCLKnFlip-FlopsComb.LogicDQSnS+LPS1+ = LS0S0+ = LP = S1S0Transition diagram is readily converted to astate transition table (just a truth table)6.111 Fall 2007 Lecture 7, Slide 4Moore Level-to-Pulse ConverterMoore FSM circuit implementation of level-to-pulse converter:outputsyk = fk(S)inputsx0...xnComb.LogicCLKnFlip-FlopsComb.LogicDQpresent state SnnextstateS+D QS1+ = LS0S0+ = LP = S1S0D QS0S1CLKS0+S1+LPQQ6.111 Fall 2007 Lecture 7, Slide 51. When L=1 and S=0, this output isasserted immediately and until thestate transition occurs (or L changes).2. While in state S=1 and as long as Lremains at 1, this output is asserted.L=1 | P=0L=1 | P=1P=00Input is low1Input is highL=0 | P=0L=0 | P=0Design of a Mealy Level-to-Pulse• Since outputs are determined by state and inputs, Mealy FSMs mayneed fewer states than Moore FSM implementationsSComb.LogicCLKFlip-FlopsComb.LogicDQnS+ndirect combinational path!PLStateClockOutput transitions immediately.State transitions at the clock edge.126.111 Fall 2007 Lecture 7, Slide 6Mealy Level-to-Pulse ConverterMealy FSM circuit implementation of level-to-pulse converter:1010LIn0010POut1010S+NextStatePres.State1100SD QSCLKS+LPQS• FSM’s state simply remembers the previous value of L• Circuit benefits from the Mealy FSM’s implicit single-cycle assertion of outputs during state transitions0Input is low1Input is highL=1 | P=1L=0 | P=0L=1 | P=0L=0 | P=06.111 Fall 2007 Lecture 7, Slide 7Moore/Mealy Trade-Offs• How are they different?– Moore: outputs = f( state ) only– Mealy outputs = f( state and input )– Mealy outputs generally occur one cycle earlier than a Moore:• Compared to a Moore FSM, a Mealy FSM might...– Be more difficult to conceptualize and design– Have fewer statesPLStateClockMealy: immediate assertion of PPLState[0]ClockMoore: delayed assertion of P6.111 Fall 2007 Lecture 7, Slide 8Light Switch RevisitedD QBUTTONLIGHTCLK01D QQLevel-to-PulseFSMLight SwitchFSM6.111 Fall 2007 Lecture 7, Slide 9FSM ExampleGOAL:Build an electronic combination lock with a resetbutton, two number buttons (0 and 1), and anunlock output. The combination should be 01011.“0”“1”RESETUNLOCKSTEPS:1.Design lock FSM (block diagram, state transitions)2.Write Verilog module(s) for FSM6.111 Fall 2007 Lecture 7, Slide 10Step 1A: Block Diagramfsm_clockresetb0_inb1_inlockbuttonbuttonbuttonClockgeneratorButtonEnterButton0Button1fsmstateunlockresetb0b1LEDDISPLAYUnlockLED6.111 Fall 2007 Lecture 7, Slide 11Step 1B: State transition diagramRESETUnlock = 0“0”Unlock = 0“01”Unlock = 0“01011”Unlock = 1“0101”Unlock = 0“010”Unlock = 00 10111010010RESET6 states → 3 bits6.111 Fall 2007 Lecture 7, Slide 12Step 2: Write Verilogmodule lock(clk,reset_in,b0_in,b1_in,out); input clk,reset,b0_in,b1_in; output out; // synchronize push buttons, convert to pulses // implement state transition diagram reg [2:0] state,next_state; always @ (*) begin // combinational logic! next_state = ???; end always @ (posedge clk) state <= next_state; // generate output assign out = ???; // debugging?endmodule6.111 Fall 2007 Lecture 7, Slide 13Step 2A: Synchronize buttons// button -- push button synchronizer and level-to-pulse converter// OUT goes high for one cycle of CLK whenever IN makes a// low-to-high transition.module button(clk,in,out); input clk; input in; output out; reg r1,r2,r3; always @ (posedge clk) begin r1 <= in; // first reg in synchronizer r2 <= r1; // second reg in synchronizer, output is in sync! r3 <= r2; // remembers previous state of button end // rising edge = old value is 0, new value is 1 assign out = ~r3 & r2; endmoduleD QD QD Qinr3r1 r2clkoutsynchronizer state6.111 Fall 2007 Lecture 7, Slide 14Step 2B: state transition diagram parameter S_RESET = 0; // state assignments parameter S_0 = 1; parameter S_01 = 2; parameter S_010 = 3; parameter S_0101 = 4; parameter S_01011 = 5; reg [2:0] state, next_state; always @ (*) begin // implement state transition diagram if (reset) next_state = S_RESET; else case (state) S_RESET: next_state = b0 ? S_0 : b1 ? S_RESET : state; S_0: next_state = b0 ? S_0 : b1 ? S_01 : state; S_01: next_state = b0 ? S_010 : b1 ? S_RESET : state; S_010: next_state = b0 ? S_0 : b1 ? S_0101 : state; S_0101: next_state = b0 ? S_010 : b1 ? S_01011 : state; S_01011: next_state = b0 ? S_0 : b1 ? S_RESET : state; default: next_state = S_RESET; // handle unused states endcase end always @ (posedge clk) state <= next_state;RESETUnlock = 0“0”Unlock = 0“01”Unlock = 0“01011 ”Unlock = 1“0101 ”Unlock = 0“010”Unlock = 00 10111010010RESET6.111 Fall 2007 Lecture 7, Slide 15Step 2C: generate output// it’s a Moore machine! Output only depends on current stateassign out = (state == S_01011);Step 2D: debugging?// hmmm. What would be useful to know? Current state?assign hex_display = {1'b0,state[2:0]};6.111 Fall 2007 Lecture 7, Slide 16Step 2: final Verilog implementationmodule lock(clk,reset_in,b0_in,b1_in,out, hex_display); input clk,reset,b0_in,b1_in; output out;
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