Radio 6.111 Final Project ReportDexter ChanDecember 14, 20051 AbstractOver the course of the last six weeks, the author attempted to implement a digital radio in Verilog with anRF fr ont end. While the author did not manage to succeed at this task, many things were learned. In thefuture, the author will not attempt to integrate digital and analog domains.1Table of Contents.1. Abstract.........................................................12. Overview.........................................................33. Description of Modules...........................................34. Testing and Debugging............................................75. Conclusion.......................................................86. Appendix.........................................................9List of Figures.Figure 1: Block Diagram......................................42antenna, amplifierassembly filterADCbroad bandpass2020to AC’97DDC14lowpass filterVGAclock_65mhz clock_27mhzclock_27mhzdividerclock_9mhzFigure 1: The block diagram, describing all parts of the system.2 OverviewOver the co urse of the previous six weeks, the author attempted to design and build a digital radio with ananalog RF re ceiving end. The project was ultimately unsuccessful; however, a great deal was learned in theprocess of building this device. Upon reflections, the author spotted many ways to improve the process.The desired goal was a system which could take as input a sig nal from an antenna and o utput the receivedsignal as sound. Later , functionality for a VGA output to graph a signal was added. The system was to betuned to the radio station WRKO, broa dcasting at 680 kilohertz. This station was one of the strongest inthe Boston area, with a transmitter power of 50 kilowatts. No user input was req uired; the signal would beoutput to the VGA display and AC’97 audio codec. This digital system was implemented via the 6.111 LabKit, containing a Xilinx Virtex 2 FPGA and a series of buttons and switches.3 Description of ModulesThe actual system consisted of several interconnected Verilog modules, as well as additional hardware hookedup to the system. These parts were the antenna, responsible for gathering a radio signal; the analog-to-digitalconverter, obtained from Analog Devices; the digital down converter, which demodulates the signal; and theVGA display, as hooked up in Figur e 1. A description of each of these modules follows.The antenna was built using a schematic provided by Ike Chuang, originally from techlib.com. The a ntennawas built using Radio Shack parts, with passive components from the Course 6 labs. The antenna had again of about 10, amplifying a 300-mv signal at the antenna base to about 3 V p eak-to-peak at the output,assuming full battery.The output from the antenna was filtered using an active filter; this was constructed out of a 741 op-amp,with two 2 2-nanofarad capacitors, a 90-ohm resistor and a 27-ohm resistor. While this filter removed the60-hertz interference from the power cables, it did not manage to transmit a radio signal at 680 kilohertz.3The analog to digital converter used was the Analog Devices 9240 evaluation board, part number 9240EB.The ADC had 14 bits of resolution and an adjustable reference voltage, which was set a ppropriately low.The ADC was capable of sampling at a maximum rate of 1 0 megahertz, which was sufficient; the minimumsampling rate to recover the entire AM band was 3.4 megahertz. The or iginal 9 mega hertz clock provedto be too high a sampling rate, as samples were being dropped at the digital down converter; the authorwas testing clocking the ADC at 1.5 megahertz (extracting samples e very 18 cycles); however, tests wereinconclusive.The digital downconverter was a built-in Xilinx module, which was implemented using the Xilinx CoreGentool. As it included a lowpass filter, the use of this module could have simplified the demodulation processgreatly. However, the author found out that he was specifying the outputs incorrec tly, which was a factorin causing the signal to display incorrectly. This will be described in further detail below.The VGA mo dule was integrated on suggestion of Jae Lee; the goal was to display an arbitrary signal on thescreen. This was largely ta ken from Ike C huang’s VGA display module, with some modifications to integrateit into the ra dio system.4 Testing and DebuggingThe author learned firsthand that redesign of a system is expensive and often painful in terms of time andcomponents. Over the cours e of this project, the author redesigned the system and revised many of hisinitial assumptions, many of which proved to be wrong.The first redesign involved rethinking the signal theory in demodulating the signal. Originally, the plan wasto use Fourier transforms to bring the signal into the frequency domain, then use hardware multipliers tofilter and demodulate. However, a fter discussion, it was determined that doing this was much more complexthan necessary, and it would suffice to multiply the incoming signal by a sine wave and pass the resultingsignal through a lowpass filter to demodulate; the r esultant wave would be passed to the audio codec.The second redesig n involved adding a VGA module on recommendation, to visualize the output. Thiswould help debug the signal as it traveled through the system. This VGA module would be connected tothe inputs of various o ther modules and graph the output.Unfortunately, rethinking the project meant that much of the previous work done was invalidated dueto incorrect inital a ssumptions. The author assumed that fast fourier transforms in hardware were fast;instead, compa red to the rest of the system, they were much slower tha n multipliers. While doing manyof the calculations in frequency space would have simplified the problem, it would introduce other designconsiderations–decreasing the sample rate of the ADC to compensate for the delay time and registering theoutputs would be some of the issues raised. Thus, the decision was made to do all calculations in the timedomain.Interfacing the analog to digital converter to the lab kit was, surprisingly, the mo st straightforward partof the system. The fact that the Analog Devices ADC took a standard IDE cable spacing was immensleyhelpful; it was not difficult to refer to the Analog Devices schematic and determine the pinout diagram forthe IDE cable. After some initial difficulty with the IDE plugs, the cable slotted smoothly into the board.The
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