OverviewPreliminary Implementation OverviewInputsTestOutput MuxcmpOutputsFPU OperationsAddition/SubtractionMultiplicationAdditional DetailsA Floating-Point Unit for Numerical CalculationsJeff Walden– 6.1115.11.06AbstractIn this project we will impl em ent a partially IEEE-754 compliantfloating-p oint unit in Veril og. The FPU will implement addition, subtrac-tion, and multiplication, and it will meet the exactness criteria specified byIEEE-754 and set exception flags as specifie d by IEEE-754. Due to timeconstraints, it will implement little of the rest of IEEE-754; however, thatwhich it implements should be sufficient for many floating-point needs.1 OverviewNumbers in computation may be divided into two categories: integers andfloating-p oint numbers. Integers are precise and exactly store mathematicalintegers purely within the bounds dictated by their width; floating-point num-bers store mathematical real numbers but even with unbounded width suffersome imprecision. This project will implement a floating-point unit supportingthe basic mathematical operations from which most floating-point operationsmay be constructed, namely addition and subtraction, multiplication, and (iftime permits) division.The implementation will aim for limited conformance with the IEEE-754standard for binary floating-point arithmetic. Rounding-mode functionality willbe limited to the round-to-nearest mode, and only single-format numbers willbe implemented. No FPU-level support will be provided for determining squareroots, calculating remainders, rounding to or from integer values, or convertingbetween bases. However, the implementation will endeavor to support accuratevalue rounding (within the limits of the single-format numbe r), positive andnegative zero and infinity, a NaN (not a number) value, and floating-point ex-ceptions, whenever possible. Deviations from the standard will be clearly notedin all reports.2 Preliminary Implem entation OverviewFor simplicity, the initial FPU implementation will consist of a mux which se-lects among the results of the set of possible calculations. This will be helpfulin getting a prototype together against which initial testing can occur. Once1a mostly-working prototype has been constructed, the design will be modifiedto accommodate faster processing on an operation-by-operation (and for spe-cial values on a value-by-value) basis. This should not be difficult to do usingsome form of tristate device, but we prefer to reason about a working but slowimplementation over reasoning about an as-yet-unrealized plan for an imple-mentation.Figure 1: A high-level diagram of the FPU2.1 InputsThe inputs to the FPU will consist of the two floating-point numbers, eachstored in 32 bits, and an operation code to indicate what calculation should beperformed. The operation co de is given in 3 bits to allow for p oss ible function-ality increases, although it is unlikely such increases will occur.2.2 TestThis block converts the external operation code into an internal code (whichmay or may not be the same). The intent of this block is to combinationallydetermine when numerical calculation can be avoided entirely (e.g., if eitheroperand is NaN, the entire operation may short-circuit). Its outputs are theaforementioned internal operation code and the two input numbers.2.3 Output MuxThe output mux selects among the various results for each of the differentfloating-p oint op e rations and determines which one is to be sent to the moduleoutputs. Its intent is to allow exactly one calculation to control the relevant2module outputs at any given time, allowing faster operations to finish beforeslower operations may have finished. It is not yet entirely clear whether thiscould be replaced with some form of tristate device, but in the likely case thatit is, doing so should allow a slight speedup in processing the faster operations.2.4 cmpComparison of floating-point numbers is relatively simple to implement, andsince a comparison requires nothing more than the bit patterns which make upthe numbers being com pared, it is calculated se parately from the main flow ofcontrol.2.5 OutputsThe outputs of the FPU are a ready flag, five exception values, the result ofthe comparison between the two input floating-point numbers, and the resultof the calculation. The ready flag allows for fast returns in the cases wherethe requested floating-point calculation is simple. The five exceptions are thosespecified by IEEE-754: invalid operation, divide by zero, overflow, underflow,and inexact. The result of the calculation will be accurate within the limits of thefloating-p oint format; in other words, the result will be the number determinedby performing the calculation exactly and using round-to-nearest to dterminethe answer.3 FPU OperationsThe implementation metho d used in calculation of each floating-point valuewill be as given in On the Design of IEEE Compliant Floating Point Units,Guy Even and Wolfgang Paul, May 2000 IEEE Transactions on Computers.This method reduces each calculation to the following steps: preprocessing eachoperand to bound precision, performing the op e ration, and rounding the resultin the correct manner while se tting exception flags as required.3.1 Addition/SubtractionThe addition algorithm consists of aligning the floating points (and thus makingthe exponents e qual), performing a sticky-bit computation (to ensure sufficientaccuracy so that during final rounding no significant data is lost), adding thenumbers (their exponents are equal, making this a relatively simple integraladdition), and rounding the final result.3.2 MultiplicationMultiplication of floating-point numbers consists of multiplying the integer dataand adding the exponents; exceptions should be the only complication in im-plementing multiplication.34 Additional DetailsIn addition to implementing the FPU, we w ill also implement a user interfaceby which interaction with the FPU is possible. We will allow the floating-pointand operation inputs to the FPU to be set, and the result and exceptions will bedisplayed in some manner for the user to view. At the moment it is unclear whatthis interface will be, but ideally the interface will consist of a small calculatorwith input given by a keyboard and with output displayed on a VGA monitor.Testing of the FPU will occur primarily through Verilog test modules. IEEE-754 verification suites will be used to verify the functionality which the FPUimplements, and a test script to
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