L12: Reconfigurable Logic ArchitecturesHistory of Computational FabricsReconfigurable LogicProgrammable Array Logic (PAL)Inside the 22v10 PALCypress PAL CE22V10Anti-Fuse-Based Approach (Actel)Actel Logic ModuleActel Routing & ProgrammingRAM Based Field Programmable Logic - XilinxThe Xilinx 4000 CLBTwo 4-input Functions, Registered Outputand a Two Input Function5-input Function, Combinational OutputLUT MappingConfiguring the CLB as a RAMXilinx 4000 InterconnectXilinx 4000 Interconnect DetailsXilinx 4000 Flexible IOBAdd Bells & WhistlesThe Virtex II CLB (Half Slice Shown)Adder ImplementationCarry ChainVirtex II FeaturesThe Latest Generation: Virtex-II ProFPGA Evolution Summary [Parlour04]Design Flow - MappingDesign Flow – Placement & RouteExample: Verilog to FPGAHow are FPGAs Used?SummaryL12: 6.111 Spring 2006 1Introductory Digital Systems LaboratoryL12: Reconfigurable Logic ArchitecturesL12: Reconfigurable Logic ArchitecturesAcknowledgements:¾ Lecture material adapted from R. Katz, G. Borriello, “Contemporary Logic Design”(second edition), Copyright 2005 Prentice-Hall/Pearson Education. ¾ Frank HonoreL12: 6.111 Spring 2006 2Introductory Digital Systems LaboratoryHistory of Computational FabricsHistory of Computational Fabrics Discrete devices: relays, transistors (1940s-50s) Discrete logic gates (1950s-60s) Integrated circuits (1960s-70s) e.g. TTL packages: Data Book for 100’s of different parts Gate Arrays (IBM 1970s) Transistors are pre-placed on the chip & Place and Route software puts the chip together automatically – only program the interconnect (mask programming) Software Based Schemes (1970’s- present) Run instructions on a general purpose core Programmable Logic (1980’s to present) A chip that be reprogrammed after it has been fabricated Examples: PALs, EPROM, EEPROM, PLDs, FPGAs Excellent support for mapping from Verilog ASIC Design (1980’s to present) Turn Verilog directly into layout using a library of standard cells Effective for high-volume and efficient use of silicon areaL12: 6.111 Spring 2006 3Introductory Digital Systems LaboratoryReconfigurable LogicReconfigurable Logic Logic blocks To implement combinationaland sequential logic Interconnect Wires to connect inputs andoutputs to logic blocks I/O blocks Special logic blocks at periphery of device forexternal connections Key questions: How to make logic blocks programmable?(after chip has been fabbed!) What should the logic granularity be? How to make the wires programmable?(after chip has been fabbed!) Specialized wiring structures for localvs. long distance routes? How many wires per logic block?LogicLogicConfigurationInputsOutputsnmQQSETCLRDL12: 6.111 Spring 2006 4Introductory Digital Systems LaboratoryProgrammable Array Logic (PAL)Programmable Array Logic (PAL) Based on the fact that any combinational logic can be realized as a sum-of-products PALs feature an array of AND-OR gates with programmable interconnectinputsignalsANDarrayOR arrayoutputsignalsprogramming of product termsprogramming of sum termsL12: 6.111 Spring 2006 5Introductory Digital Systems LaboratoryInside the 22v10 PALInside the 22v10 PAL Each input pin (and its complement) sent to the AND array OR gates for each output can take 8-16 product terms, depending on output pin “Macrocell” block provides additional output flexibility...L12: 6.111 Spring 2006 6Introductory Digital Systems LaboratoryCypress PAL CE22V10Cypress PAL CE22V10From CypressFrom Lattice SemiconductorCombinational/active lowCombinational/active high Outputs may be registered or combinational, positive or invertedL12: 6.111 Spring 2006 7Introductory Digital Systems LaboratoryAntiAnti--FuseFuse--Based Approach (Based Approach (ActelActel))Rows of programmablelogic building blocks+rows of interconnectAnti-fuse Technology:Program OnceI/O Buffers, Programming and Test LogicLogic Module Wiring TracksI/O Buffers, Programming and Test LogicI/O Buffers, Programming and Test LogicI/O Buffers, Programming and Test LogicUse Anti-fuses to buildup long wiring runs fromshort segments8 input, single output combinational logic blocksFFs constructed from discrete cross coupled gatesL12: 6.111 Spring 2006 8Introductory Digital Systems LaboratoryActelActelLogic ModuleLogic ModuleCombinational block does not have the output FFExample Gate Mapping00011011GNDABCDEYS-R Flip-FlopGNDGNDVDDRSVDD00011011QL12: 6.111 Spring 2006 9Introductory Digital Systems LaboratoryActelActelRouting & ProgrammingRouting & ProgrammingLogic ModuleOutput SegmentsLong Vertical TracksInput SegmentsOutputsInputsHorizontalChannelVppVpp/2Vpp/2GndProgramming an AntifuseAntifuseshortedVpp/2Vpp/2Vpp/2Vpp/2PrechargePhaseProgramming is Permanent (one time)L12: 6.111 Spring 2006 10Introductory Digital Systems LaboratoryRAM Based Field Programmable RAM Based Field Programmable Logic Logic --XilinxXilinxCLBCLBCLBCLBSwitchMat rixProgrammableInterconnectI/O Blocks (IOBs)ConfigurableLogic Blocks (CLBs)D QSlewRateControlPassivePull-Up,Pull-DownDel ayVccOutputBufferInputBufferQ DPad DQSDRDECS/RContr olDQSDRDECS/RContr ol11F'G'H'DINF'G'H'DINF'G'H'H'HFunc.Gen.GFunc.Gen.FFunc.Gen.G4G3G2G1F4F3F2F1C4C1C2C3 KYX H1 DIN S/R ECL12: 6.111 Spring 2006 11Introductory Digital Systems LaboratoryThe Xilinx 4000 CLBThe Xilinx 4000 CLBL12: 6.111 Spring 2006 12Introductory Digital Systems LaboratoryTwo 4Two 4--input Functions, Registered Outputinput Functions, Registered Outputand a Two Input Functionand a Two Input FunctionL12: 6.111 Spring 2006 13Introductory Digital Systems Laboratory55--input Function, Combinational Outputinput Function, Combinational OutputL12: 6.111 Spring 2006 14Introductory Digital Systems LaboratoryLUT MappingLUT Mapping N-LUT direct implementation of a truth table: any function of n-inputs. N-LUT requires 2Nstorage elements (latches) N-inputs select one latch location (like a memory)InputsWhy Latches and Not Registers?OutputLatches set by configuration bitstream4LUT exampleL12: 6.111 Spring 2006 15Introductory Digital Systems LaboratoryConfiguring the CLB as a RAMConfiguring the CLB as a RAMMemory is built using Latches not FFsRead is same a LUT Function!16x2L12: 6.111 Spring 2006 16Introductory Digital Systems LaboratoryXilinx 4000 InterconnectXilinx 4000 InterconnectL12: 6.111 Spring 2006 17Introductory Digital Systems LaboratoryXilinx 4000 Interconnect DetailsXilinx 4000 Interconnect
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