L5: Simple Sequential Circuits and VerilogKey Points from L4 (Sequential Blocks)System Timing ParametersSystem Timing (I): Minimum PeriodSystem Timing (II): Minimum DelayThe Sequential always BlockImportance of the Sensitivity ListSimulation (after Place and Route in Xilinx)Blocking vs. Nonblocking AssignmentsAssignment Styles for Sequential LogicUse Nonblocking for Sequential LogicSimulationUse Blocking for Combinational LogicThe Asynchronous Ripple CounterThe Ripple Counter in VerilogSimulation of Ripple EffectLogic for a Synchronous CounterThe 74163 Catalog CounterInside the 74163 (Courtesy TI) - Operating Modes‘163 Operating Modes - IIVerilog Code for ‘163SimulationOutput TransitionsCascading the 74163: Will this Work?Incorrect Cascade for 74163Correct Cascade for 74163SummaryL5: 6.111 Spring 2006 1Introductory Digital Systems LaboratoryL5: Simple Sequential Circuits and L5: Simple Sequential Circuits and VerilogVerilogAcknowledgements: Nathan Ickes and Rex MinL5: 6.111 Spring 2006 2Introductory Digital Systems LaboratoryKey Points from L4 (Sequential Blocks)Key Points from L4 (Sequential Blocks)Classification: Latch: level sensitive (positive latch passes input to output on high phase, hold value on low phase) Register: edge-triggered (positive register samples input on rising edge) Flip-Flop: any element that has two stable states. Quite often Flip-flop also used denote an (edge-triggered) registerDClkQQDDClkQQDPositiveRegisterPositiveLatch Latches are used to build Registers (using the Master-Slave Configuration), but are almost NEVER used by itself in a standard digital design flow. Quite often, latches are inserted in the design by mistake (e.g., an error in your Verilog code). Make sure you understand the difference between the two. Several types of memory elements (SR, JK, T, D). We will most commonly use the D-Register, though you should understand how the different types are built and their functionality.L5: 6.111 Spring 2006 3Introductory Digital Systems LaboratorySystem Timing ParametersSystem Timing ParametersDClkQInCombinationalLogicDClkQLogic Timing ParametersRegister Timing ParametersTlogic: worst case delay through the combinational logic networkTlogic,cd: contamination or minimum delay through logic networkTcq: worst case rising edge clock to q delayTcq, cd: contamination or minimum delay from clock to qTsu: setup timeTh: hold timeL5: 6.111 Spring 2006 4Introductory Digital Systems LaboratorySystem Timing (I): Minimum PeriodSystem Timing (I): Minimum PeriodDClkQInCombinationalLogicDClkQCLKTsuThTsuThTcqTcq,cdTcqTcq,cdFF1INCLoutCLoutTl,cdTsu2TlogicT > Tcq+ Tlogic+ TsuL5: 6.111 Spring 2006 5Introductory Digital Systems LaboratorySystem Timing (II): Minimum DelaySystem Timing (II): Minimum DelayDClkQInCombinationalLogicDClkQCLKTsuThThTcq,cdFF1INCLoutTl,cdTcq,cd+ Tlogic,cd> TholdCLoutL5: 6.111 Spring 2006 6Introductory Digital Systems LaboratoryThe Sequential The Sequential alwaysalwaysBlockBlock Edge-triggered circuits are described using a sequential always blockCombinational Sequentialmodule combinational(a, b, sel,out);input a, b;input sel;output out;reg out;always @ (a or b or sel) beginif (sel) out = a;else out = b;end endmodulemodule sequential(a, b, sel, clk, out);input a, b;input sel, clk;output out;reg out;always @ (posedge clk) beginif (sel) out <= a;else out <= b;end endmodule10sel10seloutaDQaoutb bclkL5: 6.111 Spring 2006 7Introductory Digital Systems LaboratoryImportance of the Sensitivity ListImportance of the Sensitivity List The use of posedge and negedge makes an always block sequential (edge-triggered) Unlike a combinational always block, the sensitivity list doesdetermine behavior for synthesis! D Flip-flop with synchronous clear D Flip-flop with asynchronous clearmodule dff_sync_clear(d, clearb, clock, q);input d, clearb, clock;output q;reg q;always @ (posedge clock) beginif (!clearb) q <= 1'b0;else q <= d; endendmodulemodule dff_async_clear(d, clearb, clock, q);input d, clearb, clock;output q;reg q;always @ (negedge clearb or posedge clock) beginif (!clearb) q <= 1’b0;else q <= d;endendmodulealways block entered only at each positive clock edgealways block entered immediately when (active-low) clearb is assertedNote: The following is incorrect syntax: always @ (clear or negedge clock)If one signal in the sensitivity list uses posedge/negedge, then all signals must. Assign any signal or variable from only one always block, Be wary of race conditions: always blocks execute in parallelL5: 6.111 Spring 2006 8Introductory Digital Systems LaboratorySimulation (after Place and Route in Xilinx)Simulation (after Place and Route in Xilinx) DFF with Synchronous Cleartc-qClear on Clock Edge DFF with Asynchronous ClearClear happens on falling edge of clearbL5: 6.111 Spring 2006 9Introductory Digital Systems LaboratoryBlocking vs. Blocking vs. NonblockingNonblockingAssignmentsAssignments1. Evaluate a | b but defer assignment of x2. Evaluate a^b^c but defer assignment of y3. Evaluate b&(~c) but defer assignment of z1. Evaluate a | b, assign result to x2. Evaluate a^b^c, assign result to y3. Evaluate b&(~c), assign result to zalways @ (a or b or c)beginx = a | b;y = a ^ b ^ c;z = b & ~c;endalways @ (a or b or c)beginx <= a | b;y <= a ^ b ^ c;z <= b & ~c;end Verilog supports two types of assignments within always blocks, with subtly different behaviors. Blocking assignment: evaluation and assignment are immediate Nonblocking assignment: all assignments deferred until all right-hand sides have been evaluated (end of simulation timestep) Sometimes, as above, both produce the same result. Sometimes, not!4. Assign x, y, and z with their new valuesL5: 6.111 Spring 2006 10Introductory Digital Systems LaboratoryAssignment Styles for Sequential LogicAssignment Styles for Sequential LogicDQDQDQin outq1 q2clkFlip-Flop Based Digital Delay Line Will nonblocking and blocking assignments both produce the desired result?module nonblocking(in, clk, out);input in, clk;output out;reg q1, q2, out;always @ (posedge clk) beginq1 <= in;q2 <= q1;out <= q2;end endmodulemodule blocking(in, clk, out);input in, clk;output out;reg q1, q2, out;always @ (posedge clk) beginq1 = in;q2 = q1;out = q2;end endmoduleL5: 6.111 Spring 2006 11Introductory Digital Systems LaboratoryUse Use NonblockingNonblockingfor Sequential Logicfor Sequential Logicalways @ (posedge clk) beginq1 = in;q2 = q1;out = q2;end
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