6.111 Fall 2006 Lecture 17, Slide 1PC+4+4*SXT(C)ASEL01Data MemoryRDWDAdrR/WWDSEL012WARc: <25:21>01XPPCJT+4InstructionMemoryADRb: <15:11>Ra: <20:16>RA2SELRc: <25:21>+RegisterFileRA1RA2RD1RD2BSEL01C: SXT(<15:0>)ZALUABJTWAWDWEALUFNControl LogicZASELBSELPCSELRA2SELWDSELALUFNWrPC+401Wr01234XAdrILLOPWASELWASELIRQWERFWERF00PCSELalways @(posedge clk) beginassign pcinc = pc + 4;module beta(clk,reset,irq,…Input [31:0] mem_data;endmoduleIf (done) $finish;for (i=0; i < 31; i = i+1) begin1.Schedule2.FSM++3.FGPAs @ HomeThe Last Lecture!6.111 Fall 2006 Lecture 17, Slide 2Schedule Reminders• Fri, 10/27: Lab #5 checkoff by 5pm• Mon, 10/30: upload CI-M Final Version by 5pmupload Project Abstract by 5pm• Wed, 11/01: Quiz, 7:30p – 9:30p, 50-340• Fri, 11/03: complete proposal meeting with TAupload Project Proposal by 5pm• Fri, 11/10: complete block diagram meeting with TA• M, Tu, W : 15min design presentations11/12–15 schedule TBA (we’ll email you!)please upload slides to website• Fri, 11/17: upload Project Checklist by 5pm• M, Tu, W : project presentations & videotaping12/11-13 schedule TBA (we’ll email you!)• Wed, 12/13: upload Final Project Report by 5pm(sorry, no extensions possible!)6.111 Fall 2006 Lecture 17, Slide 3Digital Systems = FSMs + DatapathFSM Datapath:data regsmemoriesmuxesALUscontrolstatusBut what if my FSM has hundreds or thousands of states? That’s a BIG case statement!6.111 Fall 2006 Lecture 17, Slide 4MicrosequencersProgram CounterROM orLogic+1Control SignalsStep 1: use a counter for the stateProgram CounterROM orLogic+1ControlSignalsStep 2: add a conditional branch mechanismfstatusBranch destinationBranch condition6.111 Fall 2006 Lecture 17, Slide 5Microsequencers (cont’d.)Program CounterROM orLogic+1ControlSignalsStep 3: add a (small) call/return stack to support “subroutines”fstatusCall/Branch destinationOpcode: Call/Return/Branch conditionstackpushpopSubroutine call: select destination as new PC, push PC+1 onto stackSubroutine return: select top of stack as new PC, pop stack6.111 Fall 2006 Lecture 17, Slide 6PIC Processor:Microsequencer + general-purpose datapathSource: Microchip PIC 16C5X Manual6.111 Fall 2006 Lecture 17, Slide 7PIC Instruction SetSource: Microchip PIC 16C5X Manual6.111 Fall 2006 Lecture 17, Slide 8PIC Example: Verilog// PIC corewire [9:0] pc;wire [11:0] idata;wire [3:0] porta;wire [7:0] portb;pic16c5x pic(.clk(clk),.reset(reset),.pc(pc),.idata(idata), // instruction memory.port_a_out(an[3:0]), // digit select.port_b_out(segment[7:0]), // display segments.port_c_in(sw[7:0]) // slide switches);defparam pic.PCMSB = 9; // 1024 inst locations// PIC program memory (1024 x 12): test.pictest pgm({1'b0,pc},~clk,idata);6.111 Fall 2006 Lecture 17, Slide 9PIC Example: test.picsw equ h'0018'digit equ h'0019'count equ h'001A'Start movlw 0tris PORTA ; ports A and B are outputstris PORTBmovlw h'ff'tris PORTC ; port C are inputsmovlw h'f'movwf PORTAclrf countLoopmovlw h'f'movwf PORTAmovf PORTC,0 ; read switches into Wmovwf swandlw h'f' ; keep low 4 bitscall Segmentsmovwf PORTB ; set up segmentsmovlw h'e'movwf PORTA ; turn on AN[0]buzz1decfsz count,1 ; display this digit for a whilegoto buzz1…6.111 Fall 2006 Lecture 17, Slide 10A “Real” Processor: the Beta!PC+4+4*SXT(C)ASEL01Data MemoryRDWDAdrR/WWDSEL012WARc: <25:21>01XPPCJT+4InstructionMemoryADRb: <15:11>Ra: <20:16>RA2SELRc: <25:21>+RegisterFileRA1 RA2RD1 RD2BSEL01C: SXT(<15:0>)ZALUABJTWAWDWEALUFNControl LogicZASELBSELPCSELRA2SELWDSELALUFNWrPC+401Wr01234XAdrILLOPWASELWASELIRQWERFWERF00PCSELIs this 6.004?????6.111 Fall 2006 Lecture 17, Slide 11Beta Instructions - IunusedRbRaRc10xxxx10 015 1120 1625 2131 26OP(Ra,Rb,Rc): Reg[Rc] ← Reg[Ra] op Reg[Rb]Opcodes: ADD (plus), SUB (minus), MUL (multiply), DIV (divided by),AND (bitwise and), OR (bitwise or), XOR (bitwise exclusive or)CMPEQ (equal), CMPLT (less than), CMPLE (less than or equal) [result = 1 if true, 0 if false]SHL (left shift), SHR (right shift w/o sign extension), SRA (right shift w/ sign extension)literal (two’s complement)RaRc11xxxx15 020 1625 2131 26OPC(Ra,literal,Rc): Reg[Rc] ← Reg[Ra] op SEXT(literal)Opcodes:ADDC (plus), SUBC (minus), MULC (multiply), DIVC (divided by)ANDC (bitwise and), ORC (bitwise or), XORC (bitwise exclusive or)CMPEQC (equal), CMPLTC (less than), CMPLEC (less than or equal) [result = 1 if true, 0 if false]SHLC (left shift), SHRC (right shift w/o sign extension), SRAC (right shift w/ sign extension)6.111 Fall 2006 Lecture 17, Slide 12Beta Instructions - IIliteral (two’s complement)RaRc01xxxx15 020 1625 2131 26LD(Ra,literal,Rc): Reg[Rc] ← Mem[Reg[Ra] + SEXT(literal)]ST(Rc,literal,Ra): Mem[Reg[Ra] + SEXT(literal)] ← Reg[Rc]JMP(Ra,Rc): Reg[Rc] ← PC + 4; PC ← Reg[Ra]BEQ/BF(Ra,label,Rc): Reg[Rc] ← PC + 4; if Reg[Ra] = 0 then PC ← PC + 4 + 4*SEXT(literal)BNE/BT(Ra,label,Rc): Reg[Rc] ← PC + 4;if Reg[Ra] ≠ 0 then PC ← PC + 4 + 4*SEXT(literal)LDR(label,Rc): Reg[Rc] ← Mem[PC + 4 + 4*SEXT(literal)]6.111 Fall 2006 Lecture 17, Slide 13Beta Control Logic OP OPC LD ST JMP BEQ BNE LDR Illop trap ALUFN F(op) F(op) “+” “+” — — — “A” — — WERF 1 1 1 0 1 1 1 1 1 1 BSEL 0 1 1 1 — — — — — — WDSEL 1 1 2 — 0 0 0 2 0 0 WR 0 0 0 1 0 0 0 0 0 0 RA2SEL 0 — — 1 — — — — — — PCSEL 0 0 0 0 2 Z ? 1 : 0 Z ? 0 : 1 0 3 4 ASEL 0 0 0 0 — — — 1 — — WASEL 0 0 0 — 0 0 0 0 1 16.111 Fall 2006 Lecture 17, Slide 14Beta2 (see attached sheet)• 2-stage pipeline, 1 annuled branch delay slot• Memory ops (LD, LDR, ST) take two cycle in EXE stage: addr computed in 1stcycle, memory access made in 2nd• Branch and LDR address arithmetic performed in ALU• JMP routed thru ALU• Single memory port shared by inst. fetch and memory access6.111 Fall 2006 Lecture 17, Slide 15Xilinx Synchronous Block MemorySource: Xilinx App Note 463BRAMSingle-portConfig.CLKWEAddressData_inData_out6.111 Fall 2006 Lecture 17, Slide 16InstructionPipelineDiagram100: LD(R31,6004,R2)104: ADDC(R2,47,R2)108: ST(R2,44,R31)10C: XORC(R2,-1,R2)110: ……6004: 123100 104 6004 108 10C 44 110LD ADDC 123 ST XORC 170 …LD ADDC* ADDC ST XORC* XORC …170………………CLKAddressData_outData_inMWEEXE stage inst.msel* Stalled in pipeline6.111 Fall 2006 Lecture 17, Slide 17beta2.vmodule
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