6.111 Fall 2004 Lecture 5, Slide 1Something We Can’t Build (Yet)What if you were given the following design specification:When the button is pushed:1) Turn on the light ifit is off2) Turn off the light ifit is onThe light should changestate within a secondof the button pressbuttonlightWhat makes this circuit so differentfrom those we’ve discussed before?1. “State” – i.e. the circuit has memory2. The output was changed by a input“event” (pushing a button) ratherthan an input “value”6.111 Fall 2004 Lecture 5, Slide 2Digital StateOne model of what we’d like to buildPlan: Build a Sequential Circuit with stored digital STATE –• Memory stores CURRENT state, produced at output• Combinational Logic computes• NEXT state (from input, current state)• OUTPUT bit (from input, current state)• State changes on LOAD control inputCombinationalLogicCurrentStateNewStateInput OutputMemoryDeviceLOAD6.111 Fall 2004 Lecture 5, Slide 3Storage: Using FeedbackIDEA: use positive feedback to maintain storage indefinitely. Our logic gates are built to restore marginal signal levels, so noise shouldn’t be a problem!VINVOUTResult: a bistablestorage elementFeedback constraint:VIN= VOUTVTC for inverter pairVINVOUTThree solutions: two end-points are stable middle point is unstableNot affectedby noiseWe’ll get back to this!6.111 Fall 2004 Lecture 5, Slide 4YSBSettable Storage ElementIt’s easy to build a settable storage element (called a latch) using a lenient MUX:01G0011D----01QIN01----QOUT0101“state” signalappears as bothinput and outputQ follows DQ stableADGQHere’s a feedback path,so it’s no longer acombinational circuit.6.111 Fall 2004 Lecture 5, Slide 5New Device: D LatchGDQDTPDV1 V2V2V1TPDGQG=1:Q follows DG=0:Q holdsG=1: Q Follows D, independently of Q’G=0: Q Holds stable Q’, independently of DY01ADGQQ’BUT… A change in D or G contaminates Q, hence Q’… how can this possibly work?6.111 Fall 2004 Lecture 5, Slide 6Dynamic Discipline for our latch:D StableD-Latch timingY01ADGQTo reliably latch V2:Q’• Apply V2 to D, holding G=1• After another TPD, Q’ & D both valid for TPD; will hold Q=V2 independently of G• Set G=0, while Q’ & D hold Q=D• After TPD, V2 appears at Q=Q’• After another TPD, G=0 and Q’are sufficient to hold Q=V2 independently of DDGQV2V2TPDTPDTSETUPTHOLDTPDTSETUP= 2TPD: interval prior to G transition for which D must be stable & validTHOLD= TPD: interval following G transition for which D must be stable & valid6.111 Fall 2004 Lecture 5, Slide 7NOR-based Set-Reset (SR) FlipflopSQRQSRQQForbidden StateQRSQQ00Q101001010110ResetHoldSet SetResetRSQQ??Flip-flop refers to a bi-stable element6.111 Fall 2004 Lecture 5, Slide 8Lets try using the D-Latch…CombinationalLogicGDQCurrentStateNewStateInput OutputPlan: Build a Sequential Circuit with one bit of STATE –• Single latch holds CURRENT state• Combinational Logic computes• NEXT state (from input, current state)• OUTPUT bit (from input, current state)• State changes when G = 1 (briefly!)What happens when G=1?6.111 Fall 2004 Lecture 5, Slide 9Combinational CyclesCombinationalLogicGDQCurrentStateNewStateInput OutputWhen G=1, latch is Transparent…… provides a combinational path from D to Q.Can’t work without tricky timing constrants on G=1 pulse:• Must fit within contamination delay of logic• Must accommodate latch setup, hold timesWant to signal an INSTANT, not an INTERVAL…Looks like a stupidApproach to me…16.111 Fall 2004 Lecture 5, Slide 10Edge-triggered D-RegisterGDQGDQDQDCLKQDCLKQmaster slaveObservations: only one latch “transparent” at any time: master closed when slave is open slave closed when master is open→ no combinational path through flip flop Q only changes shortly after 0 →1transition of CLK, so flip flop appearsto be “triggered” by rising edge of CLKThe gate of this latch is open when the clock is lowThe gate of this latch is open when the clock is highWhat does that one do?0101SDGQ(the feedback path in one of the master or slave latches is always active)Transitions mark instants, not intervals6.111 Fall 2004 Lecture 5, Slide 11D-Register WaveformsGDQGDQDQDCLKQDCLKQmaster slaveDCLKQmaster closedslave openslave closedmaster open6.111 Fall 2004 Lecture 5, Slide 12Um, about that hold time…GDQGDQDQmaster slaveCLKConsider HOLD TIME requirement for slave:• Negative (1 →0) clock transition → slave freezes data:• SHOULD be no output glitch, since master held constant data; BUT• master output contaminated by change in G input!• HOLD TIME of slave not met, UNLESS we assume sufficient contamination delay in the path to its D input!Accumulated tCDthru inverter, G → Q path of master must cover slave tHOLDfor this design to work!The master’s contaminationdelay must meet the holdtime of the slave6.111 Fall 2004 Lecture 5, Slide 13D-Register Timing - ICLKDQDQDCLKQ<tPDtPD: maximum propagation delay, CLK →Q>tCDtCD: minimum contamination delay, CLK →Q>tSETUPtSETUP: setup timeguarantee that D has propagated through feedback path before master closes>tHOLDtHOLD: hold timeguarantee master is closed and data is stable before allowing D to changeValues determined from master latchValues determined from slave latch6.111 Fall 2004 Lecture 5, Slide 14D-Register Timing - IICLKt1t1= tCD,reg1+ tCD,1> tHOLD,reg21DQ DQCLKreg1reg2Questions for register-based designs:• how much time for useful work (i.e. for combinational logic delay)?• does it help to guarantee a minimum tCD? How about designing registers so thattCD,reg> tHOLD,reg?• what happens if CLK signal doesn’t arrive at the two registers at exactly the same time (a phenomenon known as “clock skew”)?t2t2= tPD,reg1+ tPD,1< tCLK-tSETUP,reg26.111 Fall 2004 Lecture 5, Slide 15Sequential Circuit TimingQuestions:• Constraints on TCDfor the logic?• Minimum clock period?• Setup, Hold times for Inputs?CombinationalLogicCurrentStateNewStateInput OutputClocktCD,L= ?tPD,L= 5nstCD,R= 1nstPD,R= 3nstS,R= 2nstH,R= 2ns> 1 ns> 10 ns (TPD,R+TPD,L+ TS,R)TS= TPD,L+TS,RTH= TH,R -TCD,LThis is a simple Finite State Machine… more on next time!6.111 Fall 2004 Lecture 5, Slide 16The Sequential always Block• Edge-triggered circuits are described using a sequential always blockmodule combinational(a, b, sel,out);input a, b;input sel;output out;reg out;always @ (a or b or sel) beginif (sel) out = a;else out = b;end endmodulemodule sequential(a, b, sel, clk,
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