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5.1 Appendix : Simulations Control Unit: Code: reset = 1'b1; #20 reset = 0; action = 2'b01; #20 extracted = 1'b1; Simulation: MEM_ ADD: Code: reset = 1'b1; #10 reset = 0; #10; start = 1'b1; #10 begin start = 1'b0; feature0 = 16'd2; end #10 feature0 = 0; #10 feature0 = 16'd4; #10 feature0 = 16'd9; Simulation:MEM_ID : Code: reset = 1'b1; #20 reset = 0; #10 start = 1'b1; #10 start = 0; #30 data_out0 = 16'd84; #30 data_out0 = 16'd3; Simulation:Validation: Code: reset = 1'b1; #20 reset = 0; start = 1'b1; dis_count = 2'b01; user0 = 48'h0000_0000_000f_ffff; user1 = 48'h0000_0000_0000_000f; user2 = 48'h0000_0000_0000_0000; user3 = 48'h0000_0000_0000_0000; #10 start = 0; Simulation:Mem Test: Code: addr = 10'b00_0000_1000; din = 16'hfcfc; we = 1'b1; #10; addr = 10'b00_0000_0001; din = 16'haaaa; we = 1'b1; #10; addr = 10'b00_0000_0000; din = 16'h1111; we = 1'b1; #10 addr = 10'b10_0000_0000; din = 16'h0000; we = 1'b0; #10 addr = 10'b00_1000_0000; din = 16'h0000; we = 1'b0; #10 addr = 10'b00_0000_1000; din = 16'h0000; we = 1'b0; #10 addr = 10'b00_0000_0001; din = 16'h0000; we = 1'b0; Simuation:5.2 Appendix : Code Labkit Code: Provided by 6.111, modified by Raiza Muñiz /////////////////////////////////////////////////////////////////////////////// // // 6.111 FPGA Labkit -- Lab 4: Pong // // // Created: March 15, 2007 // Author: Nathan Ickes // // This is a template for implementing the Pong game for Lab 4. This file // includes two modules: // // - labkit: the top-level labkit module // - debounce: the synchronize/debounce module // // Students should modify and add modules according to the directions outlined // in the lab 4 manual. // /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// // // 6.111 FPGA Labkit -- Template Toplevel Module for Lab 4 (Spring 2007) // // // Created: March 15, 2007 // Author: Nathan Ickes // /////////////////////////////////////////////////////////////////////////////// module labkit (beep, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch, ac97_bit_clock, vga_out_red, vga_out_green, vga_out_blue, vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync, vga_out_vsync, tv_out_ycrcb, tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset, tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff,tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock, ram0_data, ram0_address, ram0_adv_ld, ram0_clk, ram0_cen_b, ram0_ce_b, ram0_oe_b, ram0_we_b, ram0_bwe_b, ram1_data, ram1_address, ram1_adv_ld, ram1_clk, ram1_cen_b, ram1_ce_b, ram1_oe_b, ram1_we_b, ram1_bwe_b, clock_feedback_out, clock_feedback_in, flash_data, flash_address, flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_sts, flash_byte_b, rs232_txd, rs232_rxd, rs232_rts, rs232_cts, mouse_clock, mouse_data, keyboard_clock, keyboard_data, clock_27mhz, clock1, clock2, disp_blank, disp_data_out, disp_clock, disp_rs, disp_ce_b, disp_reset_b, disp_data_in, button0, button1, button2, button3, button_enter, button_right, button_left, button_down, button_up, switch, led, user1, user2, user3, user4, daughtercard, systemace_data, systemace_address, systemace_ce_b, systemace_we_b, systemace_oe_b, systemace_irq, systemace_mpbrdy, analyzer1_data, analyzer1_clock, analyzer2_data, analyzer2_clock, analyzer3_data, analyzer3_clock, analyzer4_data, analyzer4_clock); output beep, audio_reset_b, ac97_synch, ac97_sdata_out; input ac97_bit_clock, ac97_sdata_in; output [7:0] vga_out_red, vga_out_green, vga_out_blue;output vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync, vga_out_vsync; output [9:0] tv_out_ycrcb; output tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset; input [19:0] tv_in_ycrcb; input tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff; output tv_in_i2c_clock, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock; inout tv_in_i2c_data; inout [35:0] ram0_data; output [18:0] ram0_address; output ram0_adv_ld, ram0_clk, ram0_cen_b, ram0_ce_b, ram0_oe_b, ram0_we_b; output [3:0] ram0_bwe_b; inout [35:0] ram1_data; output [18:0] ram1_address; output ram1_adv_ld, ram1_clk, ram1_cen_b, ram1_ce_b, ram1_oe_b, ram1_we_b; output [3:0] ram1_bwe_b; input clock_feedback_in; output clock_feedback_out; inout [15:0] flash_data; output [23:0] flash_address; output flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_byte_b; input flash_sts; output rs232_txd, rs232_rts; input rs232_rxd, rs232_cts; input mouse_clock, mouse_data, keyboard_clock, keyboard_data; input clock_27mhz, clock1, clock2; output disp_blank, disp_clock, disp_rs, disp_ce_b, disp_reset_b; input disp_data_in; output disp_data_out; input button0, button1, button2, button3, button_enter, button_right, button_left, button_down, button_up;input [7:0] switch; output [7:0] led; inout [31:0] user1, user2, user3, user4; inout [43:0] daughtercard; inout [15:0] systemace_data; output [6:0] systemace_address; output systemace_ce_b, systemace_we_b, systemace_oe_b; input systemace_irq, systemace_mpbrdy; output [15:0] analyzer1_data, analyzer2_data, analyzer3_data, analyzer4_data; output analyzer1_clock, analyzer2_clock, analyzer3_clock, analyzer4_clock; //////////////////////////////////////////////////////////////////////////// // // I/O Assignments //
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