Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 – Introductory Digital Systems Laboratory Problem Set 3 Problem Set Issued: February 29, 2008 Problem Set Due: March 12, 2008 Problem 1: Critical Path Timing Analysis The Figure below is the 16-bit carry-bypass adder from Lecture 8. We have removed the mux from the last stage to avoid confusion. Figure 1: Carry-bypass adder Assume the following delay for each gate: Producing Pi, Gi from Ai, Bi: 1 unit Pi, Gi, Ci to Co or Sum for a FA: 1 unit 2:1 mux delay: 1 delay unit BP: It takes 1 delay unit to generate BP from the propagate signals. What is the worst case propagation delay for the 16-bit adder? Problem 2: Two’s Complement Multiplier A 4x4 two’s complement multiplier was presented in lecture. In this problem, you will design a combinational 8x8 two’s complement multiplier in Verilog, and validate your design using a testbench. Your multiplier should take as input the two’s complement numbers X [7:0] and Y [7:0], and give as output a two’s complement number Z. How many bits will Z have? a) Code the multiplier you designed above in Verilog and validate it using a testbench. b) Implement a second two’s complement multiplier in Verilog, only this time use the signed modifier and the * operator. For this problem, turn in Verilog code for your multiplier and testbench. We also ask that you submit a screen capture of your simulation.Problem 3: Generating Block RAMs a) Generate a 16x16 Block RAM module using CoreGen. (Right click in the “Sources” window of the Xilinx ISE and select “New Source…” When presented with options for what type of source to generate, select “IP (CoreGen & Architecture Wizard)”. This will open up a core selection window. Browse through the tree structure to see all the different types of modules that can be generated. Find the option for “Single Port Block Memory” and click next, then finish. This opens a core generating wizard. Here, you can specify different parameters for the BRAM that you are going to create. All of the relevant module documentation is also available from this wizard. Adjust the width and depth parameters to specify a memory that is 16 bits wide, and uses 4 bits to address every location. Click “Generate” to finish. b) Design a module “test_mem” that writes data into one of the locations (pick any address) and then reads the data from the same location. Next, verify that the data was written correctly by running a behavioral level simulation of your testbench. Submit the Verilog code for your test module and a screenshot of your simulation. Problem 4: Introduction to Video In this problem you will build part of a video controller, and use ModelSim to verify its correct operation. To get you started, a brief overview of VGA video generation follows. For additional guidance, refer to the URL: http://www-mtl.mit.edu/Courses/6.111/labkit/vga.shtml To maintain a stable image on a monitor, a video controller must repeatedly output the entire contents of the screen, one pixel at a time, at the desired screen refresh rate (usually 60 Hz or above). This is usually accomplished by filling a memory with the desired screen image, and reading from the memory in a cyclic fashion. The screen is redrawn one row at a time, from left to right, one pixel per clock cycle. Rows are drawn from top to bottom to form a complete image. As shown in Figure 2, the total size of a video frame is somewhat wider and taller than the active video portion that is actually visible on the display. The horizontal and vertical blanking periods are artifacts from the days of CRT displays: they provide time for the electron beam to sweep back to the right/top edge of the display before starting another line/frame. To help the display synchronize with the video stream, horizontal and vertical sync signals pulse once per row redraw and once per screen redraw, respectively. The sync pulses occur roughly in the middle of the blanking periods. For a 640x480 display such as the one you will be using, the horizontal sync signal pulses 525 times per vertical sync, and the vertical sync pulses (approximately) 75 times per second to provide a screen refresh rate of 75 Hz. 2Figure 2: Geometry for a complete VGA frame Both the horizontal and vertical sync signals are high during the active video period (this is the period of time where pixels are displayed onto the screen). After the 640 visible pixels in one row, we wait 16 more clock cycles before pulling the horizontal sync signal low. This signal stays low for 96 clock cycles, after which it should be set high again. We wait another 48 clock cycles before starting to draw the next line. The blanking delays before and after the sync pulse are called the (horizontal) front porch and back porch, respectively. Together with the sync pulse itself, they form the horizontal blanking period. Figure 3: Generalized Timing Diagram for VGA Blank and Sync Signals After the horizontal blanking period of the last line of visible pixels, the vertical blanking period begins. This sequence is similar to the horizontal blanking period except that this only happens once per screen refresh (i.e. every 480 lines) and the signal lengths are expressed in lines rather than pixels. The vertical blanking period has a front porch that consists of 11 lines (8800 pixels), a sync pulse that consists of 2 lines, and a back porch that is 32 lines in length. 3Figure 4: Truth tables for the blank and sync signals, as functions of position within the frame A complete video frame consists of 525 lines of 800 pixels, for a total of 420,000 pixels. To achieve a refresh rate of 75 Hz, one pixel must be drawn every 31.75 ns. Therefore, the pixel clock frequency is 31.5 MHz. You can generate this clock signal from the labkit's built-in 27MHz clock using a Digital Clock Manager (DCM) cell in the FPGA. Complete documentation for the DCM can be found in the Xilinx Libraries Guide: http://toolbox.xilinx.com/docsan/xilinx82/books/docs/lib/lib.pdf#nameddest=DCM The labkit FPGA has twelve DCMs, and these can be used to create signals with frequencies that are multiples of a reference signal. You can instantiate a DCM in your top level module with the following lines of code: DCM pixel_clock_dcm (.CLKIN(clock_27mhz),.CLKFX(pixel_clock)); // synthesis attribute CLKFX_MULTIPLY of pixel_clock_dcm is 7
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