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MIT 6 111 - LECTURE NOTES

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Positive Edge Triggered devices Often call it /CLK because setup is when the clock signal is LOW 6.111 Lecture # 10 Topics for today: Some more details of VHDL and more examples Shift Register (as in the 74LS194) Note Lab 2 design should be done by Wednesday Page 1 VHDL Identifiers Case InsenSitivE (but best not to rely on this) First character must be a letter. Letters, Digits, and Underscores (only) Two underscores in succession are not allowed. The last character cannot be an underscore. Using reserved words is NOT allowed. Later versions of emacs use color to distinguish reserved words (and other things) Using reserved words usually provokes an understandable error comment. Legal Examples CLK, Three_StateEnable, h23, Reg_12 Illegal Examples _clk, 3_State_Enable, large#num, clk_, Three__State, register, begin Page 3 But first,… clock Conventions This is only a convention but it is widely used. What is important is when devices are triggered. Setup time here Setup time here Positive Edge Triggered devices Often call it /CLK because setup is when the clock signal is LOW Most registers are like this Negative Edge Triggered devices Often call it CLK because setup is when the clock signal is HIGH J-K flip flops tend to be like this Page 2 VHDL Reserved Words Some are abs access after begin array disconnect file guarded impure postponed rem unaffected wait There are 97: too many to remember! This is another good reason for "incremental" compilation. Start with something that compiles and add code a block at a time Page 4VHDL Values: Defined in IEEE 1164. Values you are most likely to use are '0', '1', '-', 'Z' '-' (hyphen) is 'don't care' 'Z' (MUST Be upper case) is 'High Impedance' Vectors are strings Remember VHDL is strongly typed: a+b is valid ONLY if a and b have the same length To assign to a one bit longer number (as in to accommodate overflow) c <= ('0' & a) + ('0' & b) and of course c must be defined to be one bit longer than a and b Designation of constants: '-' is a character "---" is a string (vector) of length 3 & is the concatenation operator: "01" & "111" is "01111" and so is '0' & "1111" Page 5 Packages Here is a very small package construction Entities need not be in the same file as the package declaration. library ieee; use ieee.std_logic_1164.all; entity mux2to1 is port ( a, b, sel: in std_logic; c: out std_logic); end mux2to1; architecture archmux2to1 of mux2to1 is begin c <= (a and not sel) or (b and sel); end archmux2to1; This file has the entity and architecture ibrary ieee; library and use statements use ieee.std_logic_1164.all; package mymuxpkg is component mux2to1 port ( a, b, sel: in std_logic; c: out std_logic); end component; end mymuxpkg; This file has the component declaration-- note repeated -- identical port list Page 7 library ieee; use ieee.std_logic_1164.all; use work.std_arith.all; -- needed for integer + signal entity test_tri is port(clk, oe, cnt_enb : in std_logic; data : inout std_logic_vector(7 downto 0)); Here is the use ofend test_tri; inout (tristate) architecture foo of test_tri is signal counter : std_logic_vector(7 downto 0); begin process (oe, counter) begin if (oe = '1') then data <= counter; else data <= "ZZZZZZZZ"; -- N.B. Z must be UPPERCASE! end if; end process; process (clk) begin if rising_edge(clk) then if (oe = '0') and (cnt_enb = '1') then counter <= counter + 1; end if; end if; end process; end architecture foo; Page 6 Now we can use that package in some top level code: --no, I don’t think this does anything useful… library ieee; use ieee.std_logic_1164.all; entity toplevel is port ( s: in std_logic; p, q, r: in std_logic_vector(2 downto 0); t: out std_logic_vector(2 downto 0)); end toplevel; use work.mymuxpkg.all; -- this is what we called the package architecture archtoplevel of toplevel is signal i: std_logic_vector(2 downto 0); begin -- the first two instantiations are named associations m0: mux2to1 port map (a=>i(2), b=>r(0), sel=>s, c=>t(0)); m1: mux2to1 port map (c=>t(1), b=>r(1), a=>i(1), sel=>s); -- the last instantiation is a positional association m2: mux2to1 port map (i(0), r(2), s, t(2)); i <= p and not q; end archtoplevel; Page 8Predefined Attributes s'event is read as "s tick event" where s is a signal name. rising_edge(event) is the same as (s'event and event = '1') A transaction occurs every time a signal is evaluated, whether or not the signal value changes. Evaluation of one signal can force evaluation of other signals Page 9 74LS194: Bidirectional, loadable shift register S1 S0 QA QB QC QD 1 1 A B C D Load 0 1 R QA0 QB0 QC0 Shift Right1 0 QB0 QC0 QD0 L Shift Left 0 0 QA0 QB0 QC0 QD0 Hold The part also has an asynchronous clear So now we are going to write the functionality of this part in VHDL Array Attributes are particularly useful with generic array sizes signal s : std_logic_vector(7 downto 3) s'left = 7 s'high = 7 s'right = 3 s'low = 3 s'length = 5 You can even build multiply indexed arrays: type rom is array (0 to 6, 3 down to 0) of std_logic; signal r : rom; r'left(1) = 0 r'high(1) = 6r'left(2) = 3 r'high(2) = 3 r'right(1) = 6 r'low(1) = 0r'right(2) = 0 r'low(2) = 0 r'length(1) = 7r'length(2) = 4 Page 10 --variable width shift register (like a '194) library ieee; use ieee.std_logic_1164.all; use work.std_arith.all; entity shift_reg is generic (width : integer := 4); -- to start port (data : in std_logic_vector(width-1 downto 0); -- input s: in std_logic_vector(1 downto 0); clk, sl, sr : in std_logic; -- shift bits output : out std_logic_vector (width-1 downto 0)); end shift_reg; Note that by using the generic width we could actually use this code to emulate shift registers of arbitrary width. The ‘194 is 4 bits wide The use of positional attributes makes this variable width work Page 11 Page 12-- purpose: simulation of a '194 shift register architecture first_try of shift_reg is signal int : std_logic_vector(width-1 downto 0); -- used internally constant right : std_logic_vector(1 downto 0) := "01"; constant left : std_logic_vector(1 downto 0) := "10"; constant load : std_logic_vector(1 downto 0) := "11"; constant hold : std_logic_vector(1 downto 0) := "00"; begin -- first_try output <= int; shift_reg: process(clk) begin if rising_edge(clk) then case s is when right => int <= sr & int(int'left downto int'right+1); when left => int <= int(int'left-1 downto int'right) & sl; when load => int <= data; when hold => int <= int; when others => int


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MIT 6 111 - LECTURE NOTES

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