6.111 Lecture 6I. Blocking vs. Nonblocking AssignmentsAssignment Styles for Sequential LogicUse Nonblocking for Sequential LogicUse Blocking for Combinational LogicImplementation for on/off buttonII. Single-clock Synchronous CircuitsClocked circuit for on/off buttonAsynchronous Inputs in Sequential SystemsAsynchronous Inputs in Sequential SystemsHandling MetastabilityIII. Finite State MachinesExample 1: Light SwitchExample 2: 4-bit CounterExample 2: 4-bit CounterExample 2: 4-bit CounterTwo Types of FSMsDesign Example: Level-to-PulseStep 1: State Transition DiagramStep 2: Logic DerivationStep 2: Logic DerivationMoore Level-to-Pulse ConverterMoore Level-to-Pulse ConverterDesign of a Mealy Level-to-PulseMealy Level-to-Pulse ConverterMealy Level-to-Pulse ConverterMoore/Mealy Trade-OffsFSM Timing RequirementsSummary6.111 Fall 2005 Lecture 6, Slide 16.111 Lecture 6Today:1.Blocking vs. non-blocking assignments2.Single clock synchronous circuits3.Finite State Machines6.111 Fall 2005 Lecture 6, Slide 2I. Blocking vs. Nonblocking AssignmentsConceptual need for two kinds of assignment (in always blocks):abcxyaba = bb = ax = a & by = x | cBlocking:Evaluation and assignment are immediatea <= bb <= ax <= a & by <= x | cNon-Blocking:Assignment is postponed until all r.h.s. evaluations are doneWhen to use:Sequential CircuitsCombinatorial Circuits( only in always blocks! )6.111 Fall 2005 Lecture 6, Slide 3Assignment Styles for Sequential LogicDQDQDQin outq1 q2clkFlip-Flop Based Digital Delay Line• Will nonblocking and blocking assignments both produce the desired result?module nonblocking(in, clk, out);input in, clk;output out;reg q1, q2, out;always @ (posedge clk) beginq1 <= in;q2 <= q1;out <= q2;end module blocking(in, clk, out);input in, clk;output out;reg q1, q2, out;always @ (posedge clk) beginq1 = in;q2 = q1;out = q2;end endmodule endmodule6.111 Fall 2005 Lecture 6, Slide 4Use Nonblocking for Sequential LogicDQDQDQin outq1 q2clkalways @ (posedge clk) beginq1 <= in;q2 <= q1;out <= q2;end“At each rising clock edge, q1, q2, and out simultaneously receive the old valuesof in, q1, and q2.”always @ (posedge clk) beginq1 = in;q2 = q1;out = q2;end “At each rising clock edge, q1 = in. After that, q2 = q1 = in; After that,out = q2 = q1 = in; Finally out = in.”DQinoutclkq1q2• Blocking assignments do not reflect the intrinsic behavior of multi-stage sequential logic• Guideline: use nonblocking assignments for sequentialalways blocksx <= a & b;0 1 0 1 1 x<=0Assignment completion0 1 0 01Use Blocking for Combinational Logic6.111 Fall 2005 Lecture 6, Slide 5• Nonblocking assignments do not reflect the intrinsic behavior of multi-stage combinational logic• While nonblocking assignments can be hacked to simulate correctly (expand the sensitivity list), it’s not elegant• Guideline: use blocking assignments for combinationalalways blocks(Given) Initial ConditionBlocking Behaviora b c x y1 1 0 1 1(Given) Initial Conditiona b c x y Deferred1 1 0 1 1Nonblocking Behavioralways @ (a or b or c) beginx <= a & b;y <= x | c;endalways @ (a or b or c) beginx = a & b;y = x | c;endabcxya changes; always block triggered0 1 0 1 1x = a & b;0 1 0 0 1y = x | c;0 1 0 0 0a changes; always block triggered0 1 0 1 1y <= x | c;0 1 0 1 1 x<=0, y<=16.111 Fall 2005 Lecture 6, Slide 6Implementation for on/off buttonbuttonlightmodule onoff(button,light);input button;output light;reg light;always @ (posedge button)beginlight <= ~light;endendmoduleDQBUTTONLIGHTQ6.111 Fall 2005 Lecture 6, Slide 7II. Single-clock Synchronous CircuitsWe’ll use Flip Flops and Registers – groups of FFs sharing a clock input – in a highly constrained way to build digital systems.Single-clock Synchronous Discipline:• No combinational cycles• Only care about value of combinational circuits just before rising edge of clock• Period greater than everycombinational delay• Change saved state after noise-inducing logic transitions have stopped!• Single clock signal shared among all clocked devices6.111 Fall 2005 Lecture 6, Slide 8Clocked circuit for on/off buttonmodule onoff(clk,button,light);input clk,button;output light;reg light;always @ (posedge clk)beginif (button) light <= ~light;endendmoduleDQBUTTONLIGHTCLK01QDLECLKLOAD-ENABLED REGISTERSINGLE GLOBAL CLOCKDoes this work with a 1Mhz CLK?6.111 Fall 2005 Lecture 6, Slide 9Asynchronous Inputs in Sequential SystemsWhat about external signals?Can’t guarantee setup and hold times will be met!Sequential SystemClockWhen an asynchronous signal causes a setup/hold violation...ClockQDITransition is missed on first clock cycle, but caught on next clock cycle.IITransition is caught on first clock cycle.?IIIOutput is metastablefor an indeterminate amount of time.Q: Which cases are problematic?6.111 Fall 2005 Lecture 6, Slide 10Asynchronous Inputs in Sequential SystemsAll of them can be, if more than one happens simultaneously within the same circuit.Idea: ensure that external signals directly feed exactly one flip-flopDQSequential SystemClockD QD QQ0ClockClockQ1Async InputClocked Synchronous SystemThis prevents the possibility of I and II occurring in different places in the circuit, but what about metastability?6.111 Fall 2005 Lecture 6, Slide 11Handling Metastability• Preventing metastability turns out to be an impossible problem• High gain of digital devices makes it likely that metastable conditions will resolve themselves quickly• Solution to metastability: allow time for signals to stabilizeDQComplicated Sequential Logic SystemClockDQDQLikely to be metastableright after samplingExtremely unlikely to be metastable for >2 clock cycleVery unlikely to be metastable for >1 clock cycleHow many registers are necessary?• Depends on many design parameters(clock speed, device speeds, …)• In 6.111, a pair of synchronization registers is sufficient6.111 Fall 2005 Lecture 6, Slide 12III. Finite State Machines• Finite State Machines (FSMs) are a useful abstraction for sequential circuits with centralized “states”of operation• At each clock edge, combinational logic computes outputsand next stateas a function of inputsand present stateCombinationalLogicFlip-FlopsQDinputs+presentstatenoutputs+nextstatenCLK6.111 Fall 2005 Lecture 6, Slide 13Example 1: Light Switch• State transition diagramLIGHT= 0LIGHT= 1BUTTON=1BUTTON=1BUTTON=0 BUTTON=0DQBUTTONLIGHTCLK01Combinatorial logicRegister• Logic diagram6.111 Fall 2005 Lecture 6, Slide 17Two Types of
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