L15: VLSI Integration and Performance TransformationsMoore’s LawLayout 101Custom Design/LayoutThe ASIC ApproachStandard Cell ExampleStandard Cell Layout MethodologyVerilog to ASIC Layout (the push button approach)Macro ModulesClock DistributionAnalog Circuits: Clock Frequency Multiplication (Phase Locked Loop)Scan TestingBehavioral TransformationsFixed-Coefficient MultiplicationTransform: Canonical Signed Digits (CSD)Algebraic TransformationsTransforms for Efficient Resource UtilizationRetiming Example: FIR FilterPipelining, Just Another Transformation(Pipelining = Adding Delays + Retiming)The Power of Transforms: LookaheadKey Concern in Modern VLSI: Variations!Trends: “Chip in a Day”(Matlab/Simulink to Silicon…)(courtesy of G. Qu, M. Potkonjak)L15: 6.111 Spring 20061Introductory Digital Systems LaboratoryL15: VLSI Integration and Performance L15: VLSI Integration and Performance TransformationsTransformations0.00000010.0000010.000010.00010.0010.010.1110'68'70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98'00'02$$Average Cost of one transistorGordon Moore, KeynotePresentation at ISSCC 2003Acknowledgement:Lecture material adapted from J. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits: A Design Perspective” Copyright 2003 Prentice Hall/Pearson.Curt SchurgersL15: 6.111 Spring 20062Introductory Digital Systems LaboratoryMooreMoore’’s Laws Law16151413121110987654321019591960196119621963196419651966196719681969197019711972197319741975LOG2 OF THE NUMBER OFCOMPONENTS PER INTEGRATED FUNCTIONElectronics, April 19, 1965.Source: Dataquest/Intel, 12/02Source: Dataquest/Intel, 12/02'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '0210171016101510141013101210111010109Transistors Shipped Per Year1018“…E.O. Wilson, the famous Harvard biologist who is an expert on ants, estimates that there are 10 to the 16th and 10 to the 17th ants on earth. But if you look at this curve, this year we’re making one transistor for every ant.” –Gordon Moore, “An Update on Moore’s Law”Gordon Moore, KeynotePresentation at ISSCC 2003In 1965, Gordon Moore was preparing a speech and made a memorable observation. When he started to graph data about the growth in memory chip performance, he realized there was a striking trend. Each new chip contained roughly twice as much capacity as its predecessor, and each chip was released within 18-24 months of the previous chip. If this trend continued, he reasoned, computing power would rise exponentially over relatively brief periods of time. 40048008808080858086286386486Pentium® procP60.0010.010.11101001000Transistors (MT)2X growth in 1.96 years!1970 1980 1990 2000YearCourtesy of S. Borkar (Intel)2010L15: 6.111 Spring 20063Introductory Digital Systems LaboratoryLayout 101Layout 1013-D Cross-SectionGNDVDDmetal polyp+ diffcontactfrommetalto ndiffLnWnLpWpIN OUTn-type wellp-type substratemetal/pdiffcontactn+ diffP-channel MOSFETN-channel MOSFETINOUTVDDSCircuit RepresentationGGDLayoutD Follow simple design rules (contractbetween process and circuit designers)SL15: 6.111 Spring 20064Introductory Digital Systems LaboratoryCustom Design/LayoutCustom Design/LayoutAdder stage 1WiringAdder stage 2WiringAdder stage 3Bit slice 0Bit slice 2Bit slice 1Bit slice 63Sum SelectShifterMultiplexersLoopback BusFrom register files / Cache / BypassTo register files / CacheLoopback BusLoopback BusDie photograph of the Die photograph of the Itanium integer Itanium integer datapathdatapathBitBit--slice Design Methodologyslice Design Methodology Hand crafting the layout to achieve maximum clock rates (> 1Ghz) Exploits regularity in datapath structure to optimize interconnects 9-1 Mux9-1 Mux5-1 Mux2-1 Muxck1CARRYGENSUMGEN+ LU1000umbs0s1g64sumsumbLU : LogicalUnitSUMSELato Cachenode1REGItanium has 6 integer execution units like thisItanium has 6 integer execution units like thisL15: 6.111 Spring 20065Introductory Digital Systems LaboratoryThe ASIC ApproachThe ASIC ApproachVerilog (or VHDL )Verilog (or VHDL )Logic SynthesisLogic SynthesisFloorplanningFloorplanningPlacementPlacementRoutingRoutingTape-outCircuit ExtractionCircuit ExtractionPre-Layout SimulationPre-Layout SimulationPost-Layout SimulationPost-Layout SimulationStructuralStructuralPhysicalPhysicalBehavioralBehavioralDesign CaptureDesign IterationDesign IterationMost Common Design Approach for Designs up to 500Mhz Clock RatesL15: 6.111 Spring 20066Introductory Digital Systems LaboratoryStandard Cell ExampleStandard Cell Example3-input NAND cell(from ST Microelectronics):C = Load capacitanceT = input rise/fall timePower Supply Line (VDD) Delay in (ns)!!Ground Supply Line (GND) Each library cell (FF, NAND, NOR, INV, etc.) and the variations on size (strength of the gate) is fully characterized across temperature, loading, etc.L15: 6.111 Spring 20067Introductory Digital Systems LaboratoryStandard Cell Layout MethodologyStandard Cell Layout Methodology2-level metal technology Current Day TechnologyCell-structure hidden under interconnect layers With limited interconnect layers, dedicated routing channels between rows of standard cells are needed Width of the cell allowed to vary to accommodate complexity Interconnect plays a significant role in speed of a digital circuitL15: 6.111 Spring 20068Introductory Digital Systems LaboratoryVerilogVerilogto ASIC Layout to ASIC Layout (the push button approach)(the push button approach)module adder64 (a, b, sum); input [63:0] a, b; output [63:0] sum; assign sum = a + b;endmoduleAfter SynthesisAfter RoutingAfter PlacementL15: 6.111 Spring 20069Introductory Digital Systems LaboratoryMacro ModulesMacro Modules256×32 (or 8192 bit) SRAM Generated by hard-macro module generator Generate highly regular structures (entire memories, multipliers, etc.) with a few lines of code Verilog models for memories automatically generated based on sizeL15: 6.111 Spring 200610Introductory Digital Systems LaboratoryClock DistributionClock DistributionClock skew, courtesy AlphaDQDQIBM Clock RoutingFor 1Ghz clock, skew budget is 100ps.Variations along different paths arise from:• Device: VT, W/L, etc.• Environment: VDD, °C• Interconnect: dielectric thickness variationL15: 6.111 Spring 200611Introductory Digital Systems LaboratoryAnalog Circuits: Clock Frequency Analog Circuits: Clock Frequency Multiplication (Phase Locked Loop)Multiplication (Phase Locked Loop)updownPLLIntel 486, 50MhzVCO produces
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