6.111 Final ProjectJonathan DowneyLauri KauppilaBrian MyhreProject Motivationz Distinct Sub-systemsz Complex Behavior and Architecture z FPGA Required– Not Possible with Microcontroller– Large Amount of Logicz Entertainment Valuez Appreciated by Non-Technical PeopleNES Backgroundz 1983, NES Introduced in Japanz 1985, NES released in USz 1995, Discontinued Production of NESz Nintendo sold over 62 million NES systems and 500 million gamesz Currently the most widely emulated system with over thirty different emulators.NES System Overviewz CPU: Custom 8-bit 2A03 – Based on the 6502 core running at 1.79 MHz– Onboard Audio: 2 Square Waves, 1 Triangle, 1 Digital, 1 Noise– Input from Control Padsz Main Ram: 2 KBz PPU: Picture Processing Unit – Sprite and background generation– 2 KB Video Ram– 64 Colors– 256 by 240 pixel resolutionz Removable Game Cartridges– Program Data ROM: 32KB to 1MB– Graphical Data ROM: 8KB to 1MBSchematicCPU: The Historic 6502z Designed by MOS Technologies, a division of Commodorez Released in 1975 for $25z In the first PCs such as the Commodore 64, Apple I and Apple II.z Landmark in Microprocessor design.– New “pipelining” led to no wasted memory cycles and amazing speed.– Fast Access to RAM, less registersz Efficient design of the 6502 is said to have inspired the development of the ARM processors6502 Specificsz 8-bit Bi-directional Data Busz 16-bit Address Bus (64 KB)z Complex Instruction Set with over 50 Instructionsz Eleven Addressing Modesz Operation up to 2 MHzCPU ControlInterruptControllerClockGeneratorTimingControlInstructionDecode21 MHz ClockClock 24CycleClock 1ResetReset LineReset ClearRESET_INTIRQNMIClock 2Clock 1NMI LineIRQ LineInstructionCompleteINSTRINSTRDECODEOPCODEADDRESSINGControl SignalsArithmetic Logic UnitALUInput LatchBAALU FUNCTIONRAccumulatorX IndexY IndexSEL_OPER_A SEL_OPER_B0x01BALPCHPCL012301234ALU Functions:0: A1: B2: Add3: Subtract4: AND5: OR6: XOR7: Shift A Left8: Shift A Right9: Rotate A Left10: Rotate A Right11: Shift B Left12: Shift B Right13: Rotate B Left14: Rotate B RightStack PointerAddress BusABHPCHZero PageStack PageVector PageADHBAHABHPCLReset Vector (H)Interrupt Vector (H)NMI Vector (H)Stack Pointer (S)BALADLReset Vector (L)Interrupt Vector (L)NMI Vector (L)ABH_SELABL_SELData BusOutput Data LatchTri-state Driverclk2~R/WROutInput DataLATCH_INPUT01Input Data LatchLATCH_INPUTInput DataInput LatchInstruction BufferINSTR_SELInput DataINSTR010123IRQNMIPicture Processing Unitz Works 3 times faster than CPU, a whopping 5.37 MHzz 256 x 240 resolutionz 64 colorsz Contains:– ~300 bytes of internal RAM– 2kb of external RAM (inside NES)– 8kb or more of external ROM (inside cartridge)Background Renderingz 32 x 30 “tiles” in one screenz Each tile contains 8x8 pixelsz Background rendered ~ in real timez Four steps to picture creation:1. Fetch a pattern for the tile (no color information yet)2. Fetch an “attribute” for the tile (tells what range of colors exist)3. Fetch colors from a color table4. Output pixelExample“PATTERN TABLE”……………121084…111211121191091097676532321...…………3032“NAME TABLE”… … … ……………1234567891011 12- 4 palettes for background. Each palette has 3 unique colors and a standard background colorColoringStandard background- Each 2 x 2 tile area uses the same palette. This “palette select” data is stored in an “attribute table”. - 4-bit pattern data determines what color to choose inside a paletteSprite Renderingz 64 sprites (8x8 pixel tiles) can be shown per frame. 8 sprites per line (due to time constraints)z Sprite RAM (inside PPU) contains:– 8-bit x-coordinate– 8-bit y-coordinate– Vertical/horizontal flip– Pattern table address– 2-bit palette selectionExample“PATTERN TABLE”………………Sprite memory- coordinates- pattern- attributes (flip, color)Final Outputz Background and sprite pixels are overlaid, with specific priority instructionsz Send CPU a “hit flag” for object collision, “more-than-8-sprites-on-one-line flag”PPU ArchitecturePPU Timing / Memory Accessh_blankgoes highBackground engine:128 memory fetches for real-time background renderingh_blankgoes lowSprite engine:• determines what sprites are in range for *next* scanline• outputs previously determined spritesSprite engine:finds all relevant data for in-range sprites (includes external memory fetch), and prepares output phaseBackground engine:Fetches information for first two tiles on *next* scanline0 256 320 336 340PPU Timing / Memory AccessBackground engine:Fetches memory for first two tilesSprite engine:• determines what sprites are in range for first scanline01920260261[do nothing for 1 scanline]v_blankgoes lowv_blankgoes high[repeating scanlineprocessing]Possible Extensionsz Audio Processing Unitz Ability to Load Multiple Games6.111 Final ProjectJonathan DowneyLauri KauppilaBrian
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