Radio 6.111–An FPGA Implementation of a Software RadioDexter ChanNovember 4, 2005This project intends to construct an implementation of an AM radio receiver using the Virtex II FPGA, anactivated antenna and the SA612 balanced mixer/oscillator chip. It will employ a heterody ne architecture,using an oscillator signal to filter and tune the signal from the antenna, and pass it on to the digital signalprocessing core of the system. This radio will take in RF signals of frequencies ranging from 525 kHz to 1715kHz. An ideal radio with a digital signal processing core would need to process signals at twice the highestfrequency signal it would receive; this limits our practical ability to receive signals. As the Virtex II has aneffective speed of 100 MHz, the signals that the labkit can pr ocess are theoretically limited to roughly 50MHz. This allows listening to the AM band, but no higher. This project will also explore the feasibility ofheterodyning the rece ived signal, to allow receptions of higher-frequency radio signals.It is possible to test the functionality of the system by listening to the output of the radio. There are sixmajor modules involved in constructing this cir c uit amplifier, the mixer and osc illator, the analog-digitalconverter and the digital signa l processor. There is also a minor module in the form of the antenna. Aseither hardware or Verilog implementations of many of these mo dules a lready exist, it will be possible tobootstrap this project upwards, building one module at a time while retaining functionality of the overallsystem.The antenna will simply be a length of wire, wrapped into a coil of a specific numbe r of turns and length totune it to the proper frequency. If nece ssary, this piece of equipment can be purchased or constructed withwire-wrapping tools.The amplifier can also be implemented using analog electronics; a few op-amps will be sufficient to constructthis module in hardware. It is unknown whether digital signal amplification will be adequate in this appli-cation; more research needs to be done on this topic. The amplifier will take in the signal from the tunerand amplify it; this w ill allow greater clarity in the audio output of the system.The tuner will be a simple band- pass filter, connected to the antenna; it will be keyed to the oscillatorfrequency, allowing the selection of a specific AM band. The author proposes that during the first stage ofconstruction, the tuner is implemented using off-the-shelf analog components; as other modules are com-pleted, this module will ideally be converted to a digital system. This will require moving the analog-to-digitalFigure 1: The diagram of the finite state machine.1converter farther forward in the chain, i.e. converting the signals received on all fre quencies to digital samplesand then filtering out the desired frequencies.The mixer and oscillator complete the RF receiver front end; these modules already exist in the form of theNE602 and SA612 chips. Essentially, the functionality of these chips is to convert RF signals into IF signalsthat can be pr ocessed by the rest of the FPGA.The analog-to-digital converter will sample the analog signals and convert tho se into digital information.It will be preceded by a small low-pass analog filter, to re move extraneous signals from higher frequencies.During the initial phase, the existing analog-to-digital infrastructure c an be used; eventually, it is the goal ofthis project to design our own implementation of such a unit. Further filtering can be done a t this phase, toenhance the signal, sha pe noise and deal with aliasing issues. Thus, the three separate portions of the signalprocessing unit can be an anti-aliasing filter, a noise-shaping filter and an additional amplifier. Demodulationcan be handled by the Demodulation can be ha ndled by the Real97 audio codecs; the digital samples willbe fed into the labkit’s built-in audio support.This project aims to implement at least three of the six blocks in Verilog on the Virtex II FPGA–the tuner,the digital signal proc e ssor and the analog-to-digital conver ter, plus construction of a reliable antenna. Thesethree systems are the ba re minimum required for the radio to function as a digita l system. As time andresources permit, the author would like to experiment with digital implementations of the oscillator andmixer; this may require implementing dedicated hardware to do real-time signal proc e ssing. The goal of thisproject is to complete the design and implementation of a software radio implemented on an FPGA withinfive weeks’
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