M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 6.111 Introductory Digital Systems Laboratory Fall 2009 Lecture PSet #8 Due: Thu, 10/20/09 Problem 1. Recall that in a N-bit sign-magnitude representation, the most significant bit is the sign (0 for positive, 1 for negative) and the remaining N-1 bits are the magnitude. (A) What range of numbers can be represented with an N-bit sign-magnitude number? With an N-bit two's-complement number? (B) Create a parameterized Verilog module that converts an N-bit sign-magnitude input into an N-bit two's complement output. Problem 2. Pipelining is particular form of retiming where the goal is to increase the throughput (number of results per second) of a circuit. Consider the circuit diagram below; the solid rectangles represent registers, the square are blocks of combinational logic: Each combinational block in the diagram is annotated with its propagation delay in ns. For this problem assume that the registers are "ideal", i.e., they have zero propagation delay, and zero setup and hold times. (A) What are the latency and throughput of the circuit above? Latency is how long it takes for a value in the input register to be processed and the result appear at the output register. Throughput is the number of results per second. (B) Pipeline the circuit above for maximum throughput. Pipelining adds additional registers to a circuit; we'll do this by adding additional registers at the output and then use the retiming transformation to move them between the combinational blocks. What are the latency and throughput of your resulting circuit?Problem 3. Analog to digital converters (ADC) are available with parallel or serial digital outputs. The advantage of serial output is fewer wires and interconnects but requires the added complexity of a serial to parallel conversion on the digital side. [Something to consider at project time: wires vs Verilog!] The parallel output device, however, tends to be faster. The following is a simplified diagram of each type of ADC. ParallelAD1515 data outputlines+5analoginputdatareadyconvertSerialADAnalogAD7485sdoserial data out+5analoginputmclkconvert For your 6.111 final project, you selected the AD7485, an Analog Devices 14 bit AD converter with serial output to minimize the wiring to the labkit. You prefer to write Verilog in lieu of having an additional 14 wires to your labkit. The AD converter uses a system clock, MCLK that you provide. To start the AD conversion, you assert CONVST_bar (bar = line above CONVST) low. SCO is system clock out which you can ignore for this exercise. SDO, serial data out, consists of 15 bits of data with a guaranteed resolution of 14 bits. The MSB (D14) comes out first.All timing parameters are provided in terms of t1. For the AD7485, 40ns < t1 < 100,000ns t2 (min) = t1 x 24 t3 (min) = t1 x 22. All other timing parameters can be ignored. (a) What is the maximum number of samples per second for this device? (b) The clock in the labkit, clock_27mhz, does not meet the requirements for MCLK. Write the Verilog to create the fastest clock that meets the timing requirements for MCLK. Hint: see Lecture 6. [NB. Analog Devices was founded by Ray Stata, the major contributor to the Stata Center. Analog Devices provides free samples of their products for use in 6.111 final
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