L11: 6.111 Spring 20051Introductory Digital Systems LaboratoryL11: Major/Minor L11: Major/Minor FSMsFSMs, , and RAM/ROM Instantiationand RAM/ROM InstantiationAcknowledgements: Rex MinL11: 6.111 Spring 20052Introductory Digital Systems LaboratoryQuizQuiz Quiz will be Closed Book March 14, 1:00 PM - 2:00 PMROOM: 50-340 (AKA Walker Memorial) Covers Problem Sets 1-3, Lectures 1-9 (through Arithmetic structures), Labs 1-2 Topics to be covered Combinational Logic: Boolean Algebra, Karnaugh Maps, MSP, MPS, dealing with don’t cares Latches and Edge Triggered Registers/Flip-flopsz Understand the difference between latches, registers and unclockedmemory elements (e.g., SR-Flip Flop)z Different memory types: SR, D, JK, Tz Understand setup/hold/propagation delay and how they are computed System Timing (minimum clock period and hold time constraint)z Impact of Clock skew on timing Counters and simple FSMs (understand how the ‘163 and ‘393 work) FSM design (Mealy/Moore, dealing with glitches) Combinational and sequential Verilog codingz Continuous assignments, blocking vs. non-blocking, etc.L11: 6.111 Spring 20053Introductory Digital Systems LaboratoryQuiz (cont.)Quiz (cont.) Tri-states basics Dealing with glitchesz When are glitches OK?z How do you deal with glitches in digital system design? (registered outputs, appropriate techniques to gate a clock, etc.) Memory Basicsz Understand differences between DRAM vs. SRAM vs. EEPROMz Understand timing and interfacing to the 6264 Arithmeticz Number representation: sign – magnitude, Ones complement, Twos complementz Adder Structures: Ripple carry, Carry Bypass Adder (Don’t worry about Carry lookahead adder details)z False Paths and Delay Estimationz Shift/add multiplier, Baugh-Wooley Multiplier (Twos complement multiplication)L11: 6.111 Spring 20054Introductory Digital Systems LaboratoryToward FSM ModularityToward FSM Modularity Consider the following abstract FSM:S0a1b1c1d1S1S2S3S4S5S6S7S8S9a2b2c2d2a3b3c3d3 Suppose that each set of states ax...dxis a “sub-FSM” that produces exactly the same outputs. Can we simplify the FSM by removing equivalent states?No! The outputs may be the same, but the next-state transitions are not. This situation closely resembles a procedure call or function callin software...how can we apply this concept to FSMs?L11: 6.111 Spring 20055Introductory Digital Systems LaboratoryThe Major/Minor FSM AbstractionThe Major/Minor FSM Abstraction Subtasks are encapsulated in minor FSMs with common reset and clock Simple communication abstraction: START: tells the minor FSM to begin operation (the call) BUSY: tells the major FSM whether the minor is done (the return) The major/minor abstraction is great for... Modular designs (always a good thing) Tasks that occur often but in different contexts Tasks that require a variable/unknown period of time Event-driven systemsMajor FSMMinor FSM AMinor FSM BSTARTASTARTBBUSYABUSYBCLKRESETRESETCLKL11: 6.111 Spring 20056Introductory Digital Systems LaboratoryInside the Major FSMInside the Major FSMS1S2STARTS3S4...BUSYBUSYBUSYBUSYBUSY BUSY1. Wait until the minor FSM is ready2. Trigger the minor FSM (and make sure it’s started)3. Wait until the minor FSM is doneSTARTBUSYMajor FSM StateS1S2S2S3S3S3S4CLKL11: 6.111 Spring 20057Introductory Digital Systems LaboratoryInside the Minor FSMInside the Minor FSMT2BUSYT3BUSYT4BUSY1. Wait for a trigger from the major FSM2. Do some useful workT1BUSYSTARTSTARTSTARTBUSYMajor FSM StateS1S2S2S3S3S3S4CLKMinor FSM StateT1T1T2T3T4T1T13. Signal to the major FSM that work is donecan we speed this up?L11: 6.111 Spring 20058Introductory Digital Systems LaboratoryOptimizing the Minor FSMOptimizing the Minor FSMT2BUSYT3BUSYT4BUSYT1BUSYSTARTSTARTGood idea: de-assert BUSY one cycle earlyBad idea #1:T4may not immediately return to T1T2BUSYT3BUSYT1BUSYSTARTSTARTT4BUSYBad idea #2:BUSY never asserts!T1BUSYSTARTSTARTT2BUSYL11: 6.111 Spring 20059Introductory Digital Systems LaboratoryA FourA Four--FSM ExampleFSM ExampleOperating Scenario: Major FSM is triggered by TICK Minors A and B are started simultaneously Minor C is started once both A and B complete TICKs arriving before the completion of C are ignoredMajor FSMMinor FSM AMinor FSM BSTARTASTARTBBUSYABUSYBMinor FSM CSTARTCBUSYCTICKIDLESTABSTARTASTARTBWTABTICKBUSYABUSYBTICKBUSYA+BUSYBBUSYA+BUSYBSTCSTARTCBUSYABUSYBBUSYCWTCBUSYCBUSYCBUSYCAssume that BUSYAand BUSYBboth rise before either minor FSM completes. Otherwise, we loop forever!L11: 6.111 Spring 200510Introductory Digital Systems LaboratoryFourFour--FSM Sample WaveformFSM Sample WaveformIDLE IDLESTABSTABWTABWTABWTABSTCSTCWTCWTCWTCIDLE IDLE STABstatetickSTARTABUSYASTARTBBUSYBSTARTCBUSYCMajor FSMMinor FSM AMinor FSM BSTARTASTARTBBUSYABUSYBMinor FSM CSTARTCBUSYCTICKL11: 6.111 Spring 200511Introductory Digital Systems LaboratoryUse LPM to Create ROM/RAMUse LPM to Create ROM/RAM Click on File → MegaWizard Plug-In ManagerThis starts up a series of windows so that you can specify parameters of the LPM module. You can choosez ROMz RAM dp - Dual Ported dq - Separate Inputs and Outputs io - TriState Inputs and Outputs (like the 6264)You choose the number of address bits and the word size.You should specify a file to set the values of the ROM.You can choose registered or unregistered inputs, outputs, and addresses.L11: 6.111 Spring 200512Introductory Digital Systems LaboratoryROM ContentsROM Contents Prepare a .dat file. You can type this in, write a computer program, get it from another application (speech or graphics, etc.) This has numbers separated by space.z The default base is HEX but you can use binary or decimal if you include the following statement (before the numbers).# BASE = BINARY; Insert, # SET_ADDRESS = 0; (specifies that data should start at address 0) Run dat2ntl on Athena to format your .dat file into Intel HEX for details, after ‘setup 6.111’ type ‘man dat2ntl’ dat2ntl <filename>.dat <filename>.ntlrom8x8.ntl::080000000706050403020100DC:00000001FFrom8x8.dat:# SET_ADDRESS = 0;76543210dat2ntltool on athena3ROM8addressdataSee http://web.mit.edu/6.111/www/s2005/software.html for .mif format (memory initialization format)L11: 6.111 Spring 200513Introductory Digital Systems Laboratoryrom8x8.v (generated automatically)rom8x8.v (generated automatically)//=============================================// File
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