L11/12: 6.111 Spring 2004 1Introductory Digital Systems LaboratoryL11/12: Reconfigurable Logic L11/12: Reconfigurable Logic ArchitecturesArchitecturesAcknowledgements:R. Katz, “Contemporary Logic Design”, Addison Wesley Publishing Company, Reading, MA, 1993.Frank HonoreL11/12: 6.111 Spring 2004 2Introductory Digital Systems LaboratoryHistory of Computational FabricsHistory of Computational Fabrics Discrete devices: relays, transistors (1940s-50s) Discrete logic gates (1950s-60s) Integrated circuits (1960s-70s) e.g. TTL packages: Data Book for 100’s of different parts Gate Arrays (IBM 1970s) Transistors are pre-placed on the chip & Place and Route software puts the chip together automatically – only program the interconnect (mask programming) Software Based Schemes (1970’s- present) Run instructions on a general purpose core ASIC Design (1980’s to present) Turn Verilog directly into layout using a library of standard cells Effective for high-volume and efficient use of silicon area Programmable Logic (1980’s to present) A chip that be reprogrammed after it has been fabricated Examples: PALs, EPROM, EEPROM, PLDs, FPGAs Excellent support for mapping from VerilogL11/12: 6.111 Spring 2004 3Introductory Digital Systems LaboratoryReconfigurable LogicReconfigurable Logic Logic blocks To implement combinationaland sequential logic Interconnect Wires to connect inputs andoutputs to logic blocks I/O blocks Special logic blocks at periphery of device forexternal connections Key questions: How to make logic blocks programmable?(after chip has been fabbed!) What should the logic granularity be? How to make the wires programmable?(after chip has been fabbed!) Specialized wiring structures for localvs. long distance routes? How many wires per logic block?LogicLogicConfigurationInputsOutputsnmQQSETCLRDL11/12: 6.111 Spring 2004 4Introductory Digital Systems LaboratoryProgrammable Array Logic (PAL)Programmable Array Logic (PAL) Based on the fact that any combinational logic can be realized as a sum-of-products PALs feature an array of AND-OR gates with programmable interconnectinputsignalsoutputsignalsprogramming of product termsprogramming of sum termsANDarrayOR arrayL11/12: 6.111 Spring 2004 5Introductory Digital Systems LaboratoryInside the 22v10 PALInside the 22v10 PAL Each input pin (and its complement) sent to the AND array OR gates for each output can take 8-16 product terms, depending on output pin “Macrocell” block provides additional output flexibility...L11/12: 6.111 Spring 2004 6Introductory Digital Systems LaboratoryInside the 22v10 “Inside the 22v10 “MacrocellMacrocell” Block” Block Outputs may be registered or combinational, positive or inverted Registered output may be fed back to AND array for FSMs, etc.From Lattice Semiconductorb. Combinational/active lowd. Combinational/active highCombinational/active lowCombinational/active highL11/12: 6.111 Spring 2004 7Introductory Digital Systems LaboratoryCypress PAL CE22V10Cypress PAL CE22V10L11/12: 6.111 Spring 2004 8Introductory Digital Systems LaboratoryAntiAnti--FuseFuse--Based Approach (Based Approach (ActelActel))Rows of programmablelogic building blocks+rows of interconnectAnti-fuse Technology:Program Once8 input, single output combinational logic blocksFFs constructed from discrete cross coupled gatesUse Anti-fuses to buildup long wiring runs fromshort segmentsI/O Buffers, Programming and Test LogicLogic Module Wiring TracksI/O Buffers, Programming and Test LogicI/O Buffers, Programming and Test LogicI/O Buffers, Programming and Test LogicL11/12: 6.111 Spring 2004 9Introductory Digital Systems LaboratoryActelActelLogic ModuleLogic ModuleCombinational block does not have the output FFExample Gate Mapping00011011GNDABCDEGNDGNDVDDYRSVDDQS-R Flip-Flop00011011L11/12: 6.111 Spring 2004 10Introductory Digital Systems LaboratoryActelActelRouting & ProgrammingRouting & ProgrammingLogic ModuleOutput SegmentsLong Vertical TracksInput SegmentsOutputsInputsHorizontalChannelVppVpp/2Vpp/2GndProgramming an AntifuseAntifuseshortedVpp/2Vpp/2Vpp/2Vpp/2PrechargePhaseL11/12: 6.111 Spring 2004 11Introductory Digital Systems LaboratoryRAM Based Field Programmable RAM Based Field Programmable Logic Logic --XilinxXilinxCLBCLBCLBCLBSwitchMat rixProgrammableInterconnectI/O Blocks (IOBs)ConfigurableLogic Blocks (CLBs)D QSlewRateControlPassivePull-Up,Pull-DownDel ayVccOutputBufferInputBufferQ DPad DQSDRDECS/RContr olDQSDRDECS/RContr ol11F'G'H'DINF'G'H'DINF'G'H'H'HFunc.Gen.GFunc.Gen.FFunc.Gen.G4G3G2G1F4F3F2F1C4C1C2C3 KYX H1 DIN S/R ECL11/12: 6.111 Spring 2004 12Introductory Digital Systems LaboratoryThe The XilinxXilinx4000 CLB4000 CLBL11/12: 6.111 Spring 2004 13Introductory Digital Systems LaboratoryTwo 4Two 4--input Functions, Registered Outputinput Functions, Registered Outputand a Two Input Functionand a Two Input FunctionL11/12: 6.111 Spring 2004 14Introductory Digital Systems Laboratory55--input Function, Combinational Outputinput Function, Combinational OutputL11/12: 6.111 Spring 2004 15Introductory Digital Systems LaboratoryLUT MappingLUT Mapping N-LUT direct implementation of a truth table: any function of n-inputs. N-LUT requires 2Nstorage elements (latches) N-inputs select one latch location (like a memory)4LUT exampleLatches set by configuration bitstreamInputsOutputWhy Latches and Not Registers?L11/12: 6.111 Spring 2004 16Introductory Digital Systems LaboratoryConfiguring the CLB as a RAMConfiguring the CLB as a RAMMemory is built using Latches not FFsRead is same a LUT Function!16x2L11/12: 6.111 Spring 2004 17Introductory Digital Systems LaboratoryXilinxXilinx4000 Interconnect4000 InterconnectL11/12: 6.111 Spring 2004 18Introductory Digital Systems LaboratoryXilinxXilinx4000 Interconnect Details4000 Interconnect DetailsWires are not ideal!L11/12: 6.111 Spring 2004 19Introductory Digital Systems LaboratoryAdd Bells & WhistlesAdd Bells & WhistlesHardProcessor I/OBRAMGigabit SerialMultiplierProgrammableTerminationZVCCIOZZImpedanceControlClockMgmt18 Bit18 Bit36 BitCourtesy of David B. Parlour, ISSCC 2004 Tutorial, “The Reality and Promise of Reconfigurable Computing in Digital Signal Processing”L11/12: 6.111 Spring 2004 20Introductory Digital Systems LaboratoryXilinxXilinx4000 Flexible IOB4000 Flexible IOBAdjust Transition TimeAdjust the Sampling EdgeOutputs through FF or bypassedL11/12: 6.111 Spring
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