Appendix.docAppendix GPS Top simulation GPS Top Synchronizer Serial Clock RS232 Decoder GPS FSM Wireless Reciever (VBScript) Wireless Reciever Indicator Code Identdivideren Ident Testbench Readobject Readoutside Top Identify Video Code VideoCode.pdfAppendix GPS Top simulation GPS Top module GPStop(clk, reset, data, data2, x, y, compass_in, orientation, counting, enable, data_ready, fix, state, ascii_data); input clk, reset, data, data2; input [3:0] compass_in; output[5:0] x,y; output[3:0] orientation; output fix; output [4:0] state; output counting, enable; //commmunication between serialclock and rs232 output data_ready; //communication between rs232 and gps //wire [7:0] ascii_data; //adat fom rs232 to GPS output [7:0] ascii_data; wire [7:0] ascii_data2;wire data_sync2, enable2, counting2, data_ready2, gps_ready, wireless_ready; wire [5:0] x_gps, y_gps, x_wireless, y_wireless; sync sreset(clk, reset, reset_sync); sync sdata(clk, data, data_sync); sync sdata2(clk, data2, data_sync2); sync scompass0(clk, ~compass_in[0], orientation[0]); sync scompass1(clk, ~compass_in[1], orientation[1]); sync scompass2(clk, ~compass_in[2], orientation[2]); sync scompass3(clk, ~compass_in[3], orientation[3]); serialclock sclk1(clk, reset_sync, counting, enable); serialclock sclk2(clk, reset_sync, counting2, enable2); rs232reciever xciev1(reset_sync, clk, enable, data_sync, counting, data_ready, ascii_data); rs232reciever xciev2(reset_sync, clk, enable2, data_sync2, counting2, data_ready2, ascii_data2); GPSreciever gpsmodule1(clk, reset_sync, data_ready, ascii_data, x_gps,y_gps, fix, state, gps_ready); wirelessreciever wireless1(clk, reset_sync, data_ready2, ascii_data2, x_wireless, y_wireless, wireless_ready); always @(negedge gps_ready or negedge wireless_ready) begin x <= fix ? x_gps : x_wireless; y <= fix ? y_gps : y_wireless; end endmodule Synchronizer module sync(clk, in, out);input clk, in; output out; reg r1, out; always @(posedge clk) begin r1 <= in; out <= r1; end endmodule Serial Clock module serialclock(clk, Reset_sync, counting, enable); input clk, Reset_sync, counting; output enable; //parameter clock_frequency = 27000000; // parameter baud_rate = 9600; //parameter clock_frequency = 200; //parameter baud_rate = 10; parameter cycles_per_bit = 2812; //must be even reg[12:0] count; reg enable; always @(posedge clk) begin if(Reset_sync==1) begin count <= 13'd0; enable <= 1'b0; end if (counting) begin if (count == ((cycles_per_bit/2)-1)) begin enable <= 1'b1; count <= count + 1; endelse if (count == (cycles_per_bit-1)) // else if (count == 15'd0015) count <= 13'd0; else begin count <= count+1; enable <= 1'b0; end end else begin count <= 13'd0; enable <= 1'b0; end end endmodule RS232 Decoder module rs232reciever (reset, clock, enable, data, counting, data_ready, data_out); input reset; // Active high asynchronous reset input clock; // system clock input enable; //from serial clock input data; // PS/2 data output counting; //starts serial clock output data_ready; //indicates that the data is ready output [7:0] data_out; //output [39:0] disp; // Bitmap for display (1 character) reg [7:0] keycode, data_out; reg [39:0] disp; reg [3:0] state; reg counting, data_ready, decoding, decoding2; reg [3:0] start_count; always @(posedge clock) begin if (reset) begin state <= 0; keycode <= 0; counting <= 0;data_ready <= 0; data_out <= 0; start_count <= 0; decoding <= 0; decoding2 <= 0; end else begin if(decoding == 0) begin state <= 0; data_ready <= 0; decoding2 <= 0; if(data) begin counting <= 1; if (enable) begin if (start_count[3]) start_count <= start_count; else start_count <= start_count + 1; end end else begin if (start_count[3]) begin decoding <= 1; counting <= 0; state <= 0; start_count <= 0; end else begin counting <= 1; start_count <= 0; end end end else begin data_ready <= 0; if (decoding2) if (state == 0) if (!data) counting <= 1;if (decoding2 == 0) counting <= 1; case(state) 4'd0: // Start Bit if (enable) state <= 1; 4'd1: // Bit 0 if(enable) begin keycode[0] <= data; state <= state+1; end 4'd2: if (enable) begin // Bit 1 keycode[1] <= data; state <= state+1; end 4'd3: if(enable) begin // Bit 2 keycode[2] <= data; state <= state+1; end 4'd4: if(enable) begin // Bit 3 keycode[3] <= data; state <= state+1; end 4'd5: if(enable) begin // Bit 4 keycode[4] <= data; state <= state+1; end 4'd6: if(enable) begin // Bit 5 keycode[5] <= data; state <= state+1; end 4'd7: if(enable) begin // Bit 6 keycode[6] <= data; state <= state+1; end4'd8: if(enable) begin // Bit 7 keycode[7] <= data; state <= state+1; end 4'd9: if(enable) begin // Stop bit state <= 0; counting <= 0; data_out <= keycode; data_ready <= 1; decoding2 <= 1; end endcase end end end endmodule GPS FSM module GPSreciever(clk, reset, data_ready, data_in, latminout, longminout, fix, state, position_ready); input clk, data_ready, reset; input [7:0] data_in; output [5:0] latminout, longminout; output fix; output [4:0] state; output position_ready; reg fix; reg [4:0] state; reg [4:0] count; reg [16:0] latitude_minutes_out, longitude_minutes_out; reg [5:0] latminout, longminout; reg position_ready; parameter IDLE = 0; parameter HEADER = 1; parameter TIME = 2; parameter LATDEG = 3;parameter LATMIN = 4; parameter NS = 5; parameter LONGDEG = 6; parameter LONGMIN = 7; parameter EW = 8; parameter FIX = 9; parameter SATELLITES = 10; parameter HDOP = 11; parameter ALT = 12; parameter UNITS = 13; parameter AGE = 14; parameter HEADER2 = 15; parameter HEADER3 = 16; parameter HEADER4 = 17; parameter HEADER5 = 18; parameter HEADER6 = 19; always @(posedge clk) begin if (reset) begin state <= IDLE;
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