Block RAM/ROMBlock RAMs and ROMs using Coregen(to be covered in Recitation)Block RAMs and ROMs using CoregenBlock Memory PropertiesBlock Memory PropertiesBlock Memory PropertiesBlock Memory PropertiesBlock RAM/ROM ContentsBlock RAM ModuleBlock RAM SimulationBlock RAM using Verilog CodeBlock ROM using Verilog Code (Synchronous)Block ROM using Verilog Code(Asynchronous)RAM/ROM: 6.111 Spring 20061Introductory Digital Systems LaboratoryBlock RAM/ROM Block RAM/ROM Acknowledgements: Theodoros KonstantakopoulosRAM/ROM: 6.111 Spring 20062Introductory Digital Systems LaboratoryBlock Block RAMsRAMsand ROMs using and ROMs using CoregenCoregen(to be covered in Recitation)(to be covered in Recitation) Adding a Block RAM in your Project Project → New SourceSpecify name(small letters –no numbers)SelectCoreGen IPClick “Next”RAM/ROM: 6.111 Spring 20063Introductory Digital Systems LaboratoryBlock Block RAMsRAMsand ROMs using and ROMs using CoregenCoregenChooseMemory TypeOpen FoldersClick “Next” and then “Finish” on the Next WindowRAM/ROM: 6.111 Spring 20064Introductory Digital Systems LaboratoryBlock Memory PropertiesBlock Memory PropertiesSpecify nameSelect RAM or ROMSpecifyWidth/DepthClick “Next”RAM/ROM: 6.111 Spring 20065Introductory Digital Systems LaboratoryBlock Memory PropertiesBlock Memory PropertiesAdd OptionalControl Pins(if desired)Click “Next”RAM/ROM: 6.111 Spring 20066Introductory Digital Systems LaboratoryBlock Memory PropertiesBlock Memory PropertiesSelect Polarity of Control PinsDefault is Active HighClick “Next”RAM/ROM: 6.111 Spring 20067Introductory Digital Systems LaboratoryBlock Memory PropertiesBlock Memory PropertiesClick to name a .coe file that contains initial contents (eg. for a ROM)Click “Generate” to CompleteRAM/ROM: 6.111 Spring 20068Introductory Digital Systems LaboratoryBlock RAM/ROM ContentsBlock RAM/ROM Contents .coe file looks like:Specify input radixmemory_initialization_radix=2;memory_initialization_vector=00000000, 00111110,01100011,00000011,00000011,00011110,00000011,00000011,01100011,00111110,00000000,Addr 0Addr 1Unspecified locations (if memory has more locations than givenin .coe file) are set to “0”Addr 2…..LSBMSBRAM/ROM: 6.111 Spring 20069Introductory Digital Systems LaboratoryBlock RAM ModuleBlock RAM Modulemodule ram (addr,clk,din,dout,we); input [1 : 0] addr;input clk;input [1 : 0] din;output [1 : 0] dout;input we;BLKMEMSP_V6_1 #(2, // c_addr_width………endmodule2RAM2addrdout2dinweclk Generated Module looks like:Instantiate instances in labkit.v using:ram my_bram (.addr(my_addr), .clk(my_clk), .din(my_din), .dout(my_dout),.we(my_we));RAM/ROM: 6.111 Spring 200610Introductory Digital Systems LaboratoryBlock RAM SimulationBlock RAM SimulationRegister interface:Address, data and we should be setup and held on the rising edge of clockIf we=1 on the rising edge, a write operation takes placeIf we=0 on the rising edge, a read operation takes placeRAM/ROM: 6.111 Spring 200611Introductory Digital Systems LaboratoryBlock RAM using Block RAM using VerilogVerilogCodeCode Block RAMmodule ram (addr, clk, din, dout, we); input [1 : 0] addr, din;input clk, we;output [1 : 0] dout;reg [1:0] memory[3:0]; reg [1:0] dout_r;always @(posedge clk)beginif (we) memory[addr] <= din; dout_r <= memory[addr]; endendmoduleRAM contents are initialized to “0”, by default.If for some reason you need to specify the initial contents of a RAM, then using CoreGen (instead of the Verilog code) is pretty much the only option.RAM/ROM: 6.111 Spring 200612Introductory Digital Systems LaboratoryBlock ROM using Block ROM using VerilogVerilogCode Code (Synchronous)(Synchronous) Block ROM - SynchronousROMs are inferred from case statements:module rom (clk, addr, data); input clk; input [1:0] addr; output [1:0] data; always @(posedge clk) case (addr) 2‘b00: data <= 2‘b01; 2‘b01: data <= 2‘b10; 2‘b10: data <= 2‘b11; 2‘b11: data <= 2‘b00;endcaseendmoduleUnless you have written a specific case for each address you should include in the case statement:default: data <= 2‘bXX;RAM/ROM: 6.111 Spring 200613Introductory Digital Systems LaboratoryBlock ROM using Block ROM using VerilogVerilogCodeCode(Asynchronous)(Asynchronous) Block ROMmodule rom (addr, data); input [3:0] addr; output [7:0] data; reg [7:0] dout_r;assign dout = dout_r;always @(addr) case (addr) 8'd0: dout_r <= 8'd7; 8'd1: dout_r <= 8'd6; 8'd7: dout_r <= 8'd0;endcaseendmoduleROM
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