DOC PREVIEW
MIT 6 111 - Study Guide

This preview shows page 1-2 out of 6 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 6 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 6 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 6 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

Massachusetts Institute of TechnologyDepartment of Electrical Engineering and Computer Science6.111 — Introductory Digital Systems LaboratoryFPGA Module D. E. Troxel1(April 8, 2002)(Revised: January 23, 2004)1 WARNING - BURN OUTA number of students have burned out FPGAs. The following describes the probable cause.This has not been confirmed by experiment. I really don’t want to perform this experiment.The FPGAs that have been fried are the 10K70 (the right hand one). The 10K70 is surfacemounted and it is expensive to replace. In addition, the pc board is often damaged in tryingto replace the 10K70. We have a limited number of pc boards!Altera states that unused pins MUST be unconnected. This is not possible for the pinsconnected to the AD bus (see below). In particular, you must not have the switches drivingthe AD bus unless the Flex devices are tristated for all of the AD bus pins that are drivenby the switches. Remove the jumper used to enable the switches by grounding NUSW. If indoubt, read the handout that describes the kit wiring. If you can’t find it then look for iton the web page. All of these AD bus pins must be used as inputs, outputs, or specificallytri-stated. In addition, all pins that are connected to a 50 pin connector (see below) shouldbe used as inputs, outputs, or specifically tri-stated.Unfortunately, there is no easy way to tristate unused pins. Altera literature says thatunused pins are grounded and MUST be unconnected. Unused pins must be specificallylisted in the top level entity and specifically tri-stated. See the example files tristate.acf andtristate.vhd in the directory /mit/6.111/altera/tristate/.Please use the 10K10 (on the left) until you are familiar with the use and programmingprocedures. This device is in a socket and at least we can replace it if you burn it out.2 FPGA ModuleThe FPGA module consists of two of Altera’s FLEX 10K PLDs (one FLEX 10K10 and oneFLEX 10K70) which can be accessed through the lab kit’s NuBus interface and 50-pin ribboncable connectors. The state of the NuBus interconnects can be continuously displayed onthe lab kit’s hex leds by connecting jumpers /LHEX and /HHEX to /CLK (or any otherclock). Also, the Proto strip connection labeled NUHEX must be grounded.1This document has been modified from the original version written by Brian Perrin April, 4, 2002.6.111 — FPGA Module 2Figure 1: FPGA Module Block DiagramThe 50-pin ribbon cable connectors can be fed directly into the inputs of the Logic Ana-lyzer via 50-pin connectors on the kit. Note that each gate array has its own 50-pin connectorwhich can be connected either to the K1 or K2 connectors on the kit. BEWARE, the signalswhich are grounded by the K1 and K2 connectors are different! It is never a good idea touse EDGEs of signals on the 50-pin connectors. Use only “levels” and wait for the ringingto settle down before sampling them.Most of the NuBus connections to the FPGA are to I/O pins, but one is a clock pin.Both gate arrays are driven by the same clock. Note that AD31 is used for supplyingthe clock to the CPLD module if one is also used. Thus, this should not be used by eitherFPGA if a CPLD board is used. Because of a mistake, AD1 is not connected to either FPGA.Information on the Flex devices can be found on Altera’s web site.The URL is http://altera.com/products/devices/flex10k/f10-index.html. From there, youcan click on Data Sheets and find http://altera.com/literature/lit0f10.html and then clickon the first data sheet. This tells you more than you want to know! Please don’t print itout unless you really want to save the paper copy – it is 128 pages long! Pages 5 through 15give you a good summary of capabilities.This data sheet tells you that the 10K10 has 10,000 gates and 576 logic elements whilethe 10K70 has 70,000 gates and 3744 logic elements. That is a lot of capability. Even badlywritten HDL code is likely to fit!6.111 — FPGA Module 3These FPGAs have embedded RAM so moderate sized RAMs and ROMs can be real-ized by using LPM (Library of Parameterized Modules). Click File–>MegaWizard Plug-inManager to access LPM. See the web page (click on Software Tools) for information on theformats used for embedded ROMs.3 Programming OverviewThe gate arrays are SRAM based which means they need to be configured each time poweris applied. Happily, this is done automatically as the gate arrays are wired to a flash prom(EPC2). However, one does have to program the EPC2. This is done by the Max+plusIIsoftware using information in a <project name>.pof file and communicating with the EPC2via a JTAG interface.You must generate the appropriate <project name>.pof file by selecting the appropri-ate device (EPF10K10LC84-3 or EPF10K70RC240-2 and the configuration device option ofEPC2LC20). See the beginner’s guide for details on how to do this.There is no simple (quick) way to erase the EPC2s. Instead one must “erase” them byprogramming them with an HDL file which tri-states all of the I/O pins connected to eitherthe NuBus interface or the 50-pin connector (should you ever use it). This should be donewhenever you use a new (to you) FPGA Module. Then all you need do is to program yourFPGAs. Of course you want to make sure that the two FPGAs never drive the same pin onthe NuBus interface, e.g., AD13. Appropriate files are /mit/6.111/altera/test/blank*. Alsosee /mit/6.111/altera/tristate/.4 ProgrammingThe following steps are the programming procedure:Set up your lab kit next to a computer with a programmer attached to it. The PCsrunning MAX+plusII under Windows have ByteBlasters installed.Turn on the lab kit. Insert the 10-pin ribbon connector from the programmer into the10-pin connector socket corresponding to the FLEX 10K PLD you wish to program; the leftconnector programs the FLEX 10K10, the right connector programs the FLEX 10K70. Besure the orientation of the cable in the socket is correct by lining up the notch on the socketwith the groove on the cable. The red stripe should be on your left (asumming you are infront of the kit).Using Altera’s MAX+plusII software, load the Programmer module (from the MAX+plusIImenu). If this is the first time you are using the programmer, a hardware configuration win-dow will appear. On a PC a ByteBlaster should be selected along with the parallel port6.111 — FPGA Module 4LPT1. You can edit the hardware configuration any time by clicking on Options–>HardwareSetup.To speed up the programming process turn off the


View Full Document

MIT 6 111 - Study Guide

Documents in this Course
Verilog

Verilog

21 pages

Video

Video

28 pages

Bass Hero

Bass Hero

17 pages

Deep 3D

Deep 3D

12 pages

SERPENT

SERPENT

8 pages

Vertex

Vertex

92 pages

Vertex

Vertex

4 pages

Snapshot

Snapshot

15 pages

Memories

Memories

42 pages

Deep3D

Deep3D

60 pages

Design

Design

2 pages

Frogger

Frogger

11 pages

SkiFree

SkiFree

81 pages

Vertex

Vertex

10 pages

EXPRESS

EXPRESS

2 pages

Labyrinth

Labyrinth

81 pages

Load more
Download Study Guide
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Study Guide and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Study Guide 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?