CS61C L22 Caches III (1)A Carle, Summer 2005 © UCBinst.eecs.berkeley.edu/~cs61c/su05CS61C : Machine StructuresLecture #21: Caches 32005-07-27Andy CarleCS61C L22 Caches III (2)A Carle, Summer 2005 © UCBReview: Why We Use CachesµProc60%/yr.DRAM7%/yr.110100100019801981198319841985198619871988198919901991199219931994199519961997199819992000DRAMCPU1982Processor-MemoryPerformance Gap:(grows 50% / year)Performance“Moore’s Law”• 1989 first Intel CPU with cache on chip• 1998 Pentium III has two levels of cache on chipCS61C L22 Caches III (3)A Carle, Summer 2005 © UCBReview…•Mechanism for transparent movement of data among levels of a storage hierarchy• set of address/value bindings• address => index to set of candidates• compare desired address with tag• service hit or miss- load new block and binding on missValidTag0x0-30x4-7 0x8-b 0xc-f0123...10 abcd000000000000000000 0000000001 1100address: tag index offsetCS61C L22 Caches III (4)A Carle, Summer 2005 © UCBBlock Size Tradeoff (1/3)•Benefits of Larger Block Size• Spatial Locality: if we access a given word, we’re likely to access other nearby words soon• Very applicable with Stored-Program Concept: if we execute a given instruction, it’s likely that we’ll execute the next few as well• Works nicely in sequential array accesses tooCS61C L22 Caches III (5)A Carle, Summer 2005 © UCBBlock Size Tradeoff (2/3)• Drawbacks of Larger Block Size• Larger block size means larger miss penalty- on a miss, takes longer time to load a new block from next level• If block size is too big relative to cache size, then there are too few blocks- Result: miss rate goes up• In general, minimize Average Memory Access Time (AMAT)= Hit Time + Miss Penalty x Miss RateCS61C L22 Caches III (6)A Carle, Summer 2005 © UCBBlock Size Tradeoff (3/3)•Hit Time= time to find and retrieve data from current level cache•Miss Penalty= average time to retrieve data on a current level miss (includes the possibility of misses on successive levels of memory hierarchy)•Hit Rate= % of requests that are found in current level cache•Miss Rate= 1 - Hit RateCS61C L22 Caches III (7)A Carle, Summer 2005 © UCBBlock Size Tradeoff ConclusionsMissPenaltyBlock SizeIncreased Miss Penalty& Miss RateAverageAccessTimeBlock SizeExploits Spatial LocalityFewer blocks: compromisestemporal localityMissRateBlock SizeCS61C L22 Caches III (8)A Carle, Summer 2005 © UCBTypes of Cache Misses (1/2)•“Three Cs” Model of Misses•1st C: Compulsory Misses• occur when a program is first started• cache does not contain any of that program’s data yet, so misses are bound to occur• can’t be avoided easily, so won’t focus on these in this courseCS61C L22 Caches III (9)A Carle, Summer 2005 © UCBTypes of Cache Misses (2/2)• 2nd C: Conflict Misses• miss that occurs because two distinct memory addresses map to the same cache location• two blocks (which happen to map to the same location) can keep overwriting each other• big problem in direct-mapped caches• how do we lessen the effect of these?• Dealing with Conflict Misses• Solution 1: Make the cache size bigger- Fails at some point • Solution 2: Multiple distinct blocks can fit in the same cache Index?CS61C L22 Caches III (10)A Carle, Summer 2005 © UCBFully Associative Cache (1/3)•Memory address fields:• Tag: same as before• Offset: same as before• Index: non-existant•What does this mean?• no “rows”: any block can go anywhere in the cache• must compare with all tags in entire cache to see if data is thereCS61C L22 Caches III (11)A Carle, Summer 2005 © UCBFully Associative Cache (2/3)•Fully Associative Cache (e.g., 32 B block)• compare tags in parallelByte Offset:Cache DataB 00431:Cache Tag (27 bits long)Valid:B 1B 31:Cache Tag=====:CS61C L22 Caches III (12)A Carle, Summer 2005 © UCBFully Associative Cache (3/3)•Benefit of Fully Assoc Cache• No Conflict Misses (since data can go anywhere)•Drawbacks of Fully Assoc Cache• Need hardware comparator for every single entry: if we have a 64KB of data in cache with 4B entries, we need 16K comparators: infeasibleCS61C L22 Caches III (13)A Carle, Summer 2005 © UCBThird Type of Cache Miss•Capacity Misses• miss that occurs because the cache has a limited size• miss that would not occur if we increase the size of the cache• sketchy definition, so just get the general idea•This is the primary type of miss for Fully Associative caches.CS61C L22 Caches III (14)A Carle, Summer 2005 © UCBN-Way Set Associative Cache (1/4)•Memory address fields:• Tag: same as before• Offset: same as before• Index: points us to the correct “row” (called a setin this case)•So what’s the difference?• each set contains multiple blocks• once we’ve found correct set, must compare with all tags in that set to find our dataCS61C L22 Caches III (15)A Carle, Summer 2005 © UCBN-Way Set Associative Cache (2/4)•Summary:• cache is direct-mapped w/respect to sets• each set is fully associative• basically N direct-mapped caches working in parallel: each has its own valid bit and dataCS61C L22 Caches III (16)A Carle, Summer 2005 © UCBN-Way Set Associative Cache (3/4)•Given memory address:• Find correct set using Index value.• Compare Tag with all Tag values in the determined set.• If a match occurs, hit!, otherwise a miss.• Finally, use the offset field as usual to find the desired data within the block.CS61C L22 Caches III (17)A Carle, Summer 2005 © UCBN-Way Set Associative Cache (4/4)•What’s so great about this?• even a 2-way set assoc cache avoids a lot of conflict misses• hardware cost isn’t that bad: only need N comparators•In fact, for a cache with M blocks,• it’s Direct-Mapped if it’s 1-way set assoc• it’s Fully Assoc if it’s M-way set assoc• so these two are just special cases of the more general set associative designCS61C L22 Caches III (18)A Carle, Summer 2005 © UCBAssociative Cache Example• Recall this is how a simple direct mapped cache looked.• This is also a 1-way set-associative cache!MemoryMemory Address0123456789ABCDEF4 Byte Direct Mapped CacheCache Index0123CS61C L22 Caches III (19)A Carle, Summer 2005 © UCBAssociative Cache Example• Here’s a simple 2 way set associative cache.MemoryMemory Address0123456789ABCDEFCache Index0011CS61C L22 Caches III (22)A Carle, Summer 2005 © UCBBlock Replacement Policy (1/2)•Direct-Mapped Cache:
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