3 30 11 You Are Here So ware Hardware Parallel Requests Assigned to computer e g Search Katz CS 61C Great Ideas in Computer Architecture Machine Structures FSMs and Logisim Harness Parallel Threads Parallelism Assigned to core e g Lookup Ads Achieve High Performance 1 instrucYon one Yme e g 5 pipelined instrucYons Parallel Data 1 data item one Yme e g Add of 4 pairs of words Hardware descripYons All gates funcYoning in parallel at same Yme Spring 2011 Lecture 17 1 3 30 11 Levels of RepresentaYon InterpretaYon Compiler Assembly Language Program e g MIPS lw lw sw sw Assembler Machine Language Program MIPS t0 0 2 t1 4 2 t1 0 2 t0 4 2 0000 1010 1100 0101 1001 1111 0110 1000 1100 0101 1010 0000 Anything can be represented as a number i e data or instrucYons 0110 1000 1111 1001 1010 0000 0101 1100 Core Core Memory Cache Input Output InstrucYon Unit s Core FuncYonal Unit s A0 B0 A1 B1 A2 B2 A3 B3 Main Memory Today Logic Gates Spring 2011 Lecture 17 3 Review temp v k v k v k 1 v k 1 temp High Level Language Program e g C Computer Parallel InstrucYons Instructors Randy H Katz David A PaGerson hGp inst eecs Berkeley edu cs61c sp11 3 30 11 Smart Phone Warehouse Scale Computer 1111 1001 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111 Machine Interpreta4on Hardware Architecture DescripCon e g block diagrams Architecture Implementa4on Hardware systems are constructed from Stateless CombinaYonal Logic and Stateful Memory Logic Registers Real world voltages are analog but are quanYzed to represent logic 0 and logic 1 Truth table can be mapped to gates for combinaYonal logic design Boolean algebra allows minimizaYon of gates State registers implemented from Flip ops Logic Circuit DescripCon 3 30 11 Circuit SchemaCc Diagrams Spring 2011 Lecture 17 4 3 30 11 State Elements Finite State Machines Administrivia IntroducYon to Logisim Technology Break MulYplexer ALU Design 3 30 11 Fall 2010 Lecture 23 5 Model for Synchronous Systems Agenda Spring 2011 Lecture 17 6 CollecYon of CombinaYonal Logic blocks separated by registers Feedback is opYonal Clock signal s connects only to clock input of registers Clock CLK steady square wave that synchronizes the system Register several bits of state that samples on rising edge of CLK posiYve edge triggered 3 30 11 Fall 2010 Lecture 23 7 1 3 30 11 Camera Analogy Timing Terms Want to take a portrait Yming right before and aler taking picture Set up me don t move since about to take picture open camera shuGer Hold me need to hold sYll aler shuGer opens unYl camera shuGer closes Time click to data Yme from open shuGer unYl can see image on output view nder 3 30 11 Spring 2011 Lecture 17 Setup Time when the input must be stable before the rising edge of the CLK Hold Time when the input must be stable a er the rising edge of the CLK CLK to Q Delay how long it takes the output to change measured from the rising edge of the CLK 8 3 30 11 Fall 2010 Lecture 23 9 Pipelining to Improve Performance 1 2 Maximum Clock Frequency Extra Register are olen added to help speed up the clock rate What is the maximum frequency of this circuit Timing Hint Frequency 1 Period Max Delay 3 30 11 Setup Time CLK to Q Delay CL Delay Fall 2010 Lecture 23 10 Note delay of 1 clock cycle from input to output Clock period limited by propagaYon delay of adder shiler 3 30 11 Pipelining to Improve Performance InserYon of register allows higher clock frequency 2 2 More outputs per second Timing Fall 2010 Lecture 23 11 Another Great Idea Finite State Machines FSM You may have seen FSMs in other classes Same basic idea FuncYon can be represented with a state transiYon diagram With combinaYonal logic and registers any FSM can be implemented in hardware 3 30 11 Fall 2010 Lecture 23 12 3 30 11 Fall 2010 Lecture 23 13 2 3 30 11 Example 3 Ones FSM FSM to detect the occurrence of 3 consecuYve 1 s in the Input Hardware ImplementaYon of FSM Register needed to hold a representaYon of the machine s state Unique bit paGern for each state Draw the FSM 14 Hardware for FSM CombinaYonal Logic 3 30 11 Fall 2010 Lecture 23 15 Approximate 61C Grade So Far GPA 2 85 Fall 61C 2 81 PS Input NS Output 00 0 00 0 00 1 01 0 01 0 00 0 01 1 10 0 10 0 00 0 10 1 00 1 Extra credit moves up people near boarderline e g B to B 50 C B A 40 Below C 30 Truth table Grades up to including Lab 9 20 points for full course 25 A 50 B 15 C 10 D F Can look at its funcYonal speci caYon truth table form Number of students Fall 2010 Lecture 23 10 3 30 11 The register is used to break the feedback path between NS and PS controlled by the clock 0 Assume state transiYons are controlled by the clock On each clock cycle the machine checks the inputs and moves to a new state and produces a new output CombinaYonal logic circuit is used to implement a funcYon maps from present state and input to next state and output 300 350 400 450 500 Weighted raw score as reported by glookup 3 30 11 Fall 2010 Lecture 23 16 3 30 11 Administrivia Thread Level Parallelism and OpenMP Last homework due Sunday 4 10 Project 4 Part 1 due Sunday 4 10 Part 2 4 17 Design a 16 bit pipelined computer in Logisim Labs 10 and 11 prepare for Project 4 Lab 12 Malloc Free in C Extra Credit due 4 24 Fastest Matrix MulYply Final Exam Monday 5 9 11 30 2 30PM Spring 2011 Lecture 17 17 Midway Survey Results Project 3 Part 2 due Sunday 4 3 3 30 11 Spring 2011 Lecture 17 18 Early start by email for Fall 2011 61C 70 yes 25 maybe Read textbook 33 before lectures 50 before assignment AGend lecture 80 rarely never miss Pace of lecture MapReduce lab project MIPS emulator project SaYsfactory learned some all others Get to know Prof 2 3 like do more 1 3 OK Peer instrucYon 45 liGle fast 30 just right 10 liGle slow 3 30 11 Enjoyed Learned a lot 25 wish more 55 OK Spring 2011 Lecture 17 19 3 3 30 11 61c in the News Paul Baran Internet Pioneer Dies at 84 Idea was to build a distributed communicaYons network less vulnerable to aGack or disrupYon than convenYonal networks He suggested that The Internet is really the work networks be designed with of a thousand people redundant routes so that if a In the early 1960s he outlined parYcular path failed or was the fundamentals for destroyed messages could sYll packaging data into discrete be delivered through another bundles which he called When he approached AT T message blocks The bundles with the idea to …
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