inst eecs berkeley edu cs61c CS61C Machine Structures Lecture 24 Latches Lecturer PSOE Dan Garcia www cs berkeley edu ddgarcia SETI Home Yak The Honeynet project uses honeypot PCs monitors how long it takes sec min for them to be hacked and what happens 1 Mebi botnets are used for spam viruses DDoS Google AdSense hacking gambling id theft news bbc co uk 2 hi technology 4354109 stm Garcia UCB CS61C L24 Latches 1 Last time Extremely Clever Subtractor unsigned overflow a b xor signed CS61C L24 Latches 2 Garcia UCB 2 Input Multiplexor MUX Review Definition Symbol A B 0 C 1 D C 0 A 1 0 B 0 D CS61C L24 Latches 3 Garcia UCB Review Use muxes to select among input S input bits selects 2S inputs Each input can be n bits wide indep of S Implement muxes hierarchically ALU can be implemented using a mux Coupled with basic block elements N bit adder subtractor done using N 1 bit adders with XOR gates on input XOR serves as conditional inverter CS61C L24 Latches 4 Garcia UCB Combinational Logic from 10 miles up CL circuits simply compute a binary function e g from truthtable Once the inputs go away the outputs go away nothing is saved no STATE X Y Similar to a function in Scheme with no set or define to save anything define xor x y Z or and not x y and x not y X Y CS61C L24 Latches 5 Garcia UCB State Circuits Overview State circuits have feedback e g in0 12 lab out1 out0 in1 counter Combinational Logic Output is function of inputs fed back signals Feedback signals are the circuit s state What aspects of this circuit might cause CS61C L24 Latches 6 Garcia UCB A simpler state circuit two inverters 0 1 0 1 0 When started up it s internally stable OR Provide an or gate for coordination S Q 1 0 0 1 CS61C L24 Latches 7 1 0 0 1 10 How do we set to 0 Garcia UCB An R S latch cross coupled NOR gates S means set to 1 R means reset to 0 R Q S OR 0 1 0 1 0 1 1 0 Q 1 0 00 1 A 0 0 1 1 NOR 1 0 0 0 Hold 0 1 TruthRS latch table Adding Q gives standard CS61C L24 Latches 8 B 0 1 0 1 S 0 0 1 1 R 0 1 0 1 Q hold keep value 0 1 unstable Garcia UCB An R S latch in detail Truth table A 0 0 1 1 B 0 1 0 1 NOR 1 0 0 0 CS61C L24 Latches 9 S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q 1 0 1 0 1 0 x x Q t t 0 hold 1 hold 0 reset 0 reset 1 set 1 set x unstable x unstable Garcia UCB R S latch in scheme It s really just recursion demo A 0 0 1 1 B 0 1 0 1 NOR 1 0 0 0 CS61C L24 Latches 10 define rs latch r s define rsl h q qbar rsl h nor r qbar nor q s rsl h t f Garcia UCB State diagram States represent possible output values Transitions represent changes between states based on inputs CS61C L24 Latches 11 SR 10 SR 00 SR 01 SR 01 Q Q 0 1 SR 01 Q Q 1 0 SR 00 SR 10 SR 10 SR 11 SR 11 SR 01 Q Q 0 0 SR 11 SR 00 SR 11 SR 00 SR 10 Q Q 1 1 Garcia UCB What does it mean to clobber midterm You STILL have to take the final even if you aced the midterm The final will contain midterm material Qs and new post midterm Qs They will be graded separately If you do better on the midterm material we will clobber your midterm with the new score If you do worse midterm unchanged What does better mean Better w r t Standard Deviations around mean What does new mean Score based on remapping St Dev score on final midterm material to midterm score St Dev CS61C L24 Latches 12 Garcia UCB Clobber the midterm example Midterm Mean 47 Standard Deviation 14 You got a 33 one below Final Midterm Material Questions Mean 40 Standard Deviation 20 You got a 60 one above Your new midterm score is now mean 47 14 61 double your old score CS61C L24 Latches 13 Garcia UCB R R Q clock Q S S Controlling R S latch with a clock Can t change R and S while clock is active A 0 0 1 1 B 0 1 0 1 NOR 1 0 0 0 Clocked latches are called flip flops CS61C L24 Latches 14 Garcia UCB D flip flop are what we really use Inputs C clock and D When C is 1 latch open output D even if it changes transparent latch When C is 0 latch closed output stored value C 0 0 1 1 D 0 1 0 1 AND 0 0 0 1 CS61C L24 Latches 15 Garcia UCB D flip flop details We don t like transparent latches We can build them so that the latch is only open for an instant on the rising edge of a clock as it goes from 0 1 D C Q Timing Diagram CS61C L24 Latches 16 Garcia UCB But do you really understand NORs If one input is 1 what is a NOR If one input is 0 what is a NOR A 0 0 1 1 B 0 1 0 1 NOR 1 0 0 0 A B BP 0 0Q 1 AD CS61C L24 Latches 17 C NOR NOR D C A NOR 0 P B 1 Q 0 Garcia UCB But do you really understand NANDs If one input is 1 what is a NAND If one input is 0 what is a NAND A 0 0 1 1 B 0 1 0 1 NAND 1 1P 1 1 0 BQ A B 0 1 AD CS61C L24 Latches 18 NAND C NAND A NAND D C 0 P 1 B 1 Q Garcia UCB Peer instruction Pick the truth table that results from substituting NAND gates for the NOR gates in the R S latch A 0 0 1 1 B 0 1 0 1 A 0 0 1 1 NOR 1 0 0 0 B 0 1 0 1 1 Q hold 0 1 undef CS61C L24 Latches 19 not Q Q B A A 0 0 1 1 B 0 1 0 1 2 Q hold 1 0 undef A 0 0 1 1 B 0 1 0 1 3 Q undef 0 1 hold A 0 0 1 1 B 0 1 0 1 NAND 1 1 1 0 A 0 0 1 1 B 0 1 0 1 Q undef 1 0 hold 4 Garcia UCB Peer Instruction A a …
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