cs 61C L25 pipeline.1Patterson Spring 99 ©UCBCS61C Introduction to PipeliningLecture 25April 28, 1999Dave Patterson(http.cs.berkeley.edu/~patterson)www-inst.eecs.berkeley.edu/~cs61c/schedule.htmlcs 61C L25 pipeline.2Patterson Spring 99 ©UCBOutline°Review Parameter Passing on Stacks°Pipelining Analogy°Pipelining Instruction Execution°Administrivia, “What’s this Stuff Bad for?”°Hazards to Pipelining°Solutions to Hazards°Advanced Pipelining Concepts by Analogy°Conclusioncs 61C L25 pipeline.3Patterson Spring 99 ©UCBReview 1/1°Every machine has a convention for howarguments are passed.°In MIPS, where do the arguments go if youare passing more than 4 words? Stack!°It is sometimes useful to have a variablenumber of arguments.• The C convention is to use “...”• *fmt is used to determine the number ofvariables and their types.cs 61C L25 pipeline.4Patterson Spring 99 ©UCBPipelining is Natural! Laundry Example° Ann, Brian, Cathy, Daveeach have one load ofclothes to wash, dry,fold, and put away° Washer takes 30minutes° Dryer takes 30 minutes° “Folder” takes 30minutes° “Stasher” takes 30minutes to put clothesinto drawersA B C Dcs 61C L25 pipeline.5Patterson Spring 99 ©UCBSequential Laundry°Sequential laundry takes8 hours for 4 loads30TaskOrderBCDATime3030 3030 30 3030 3030 3030 3030 30306 PM78910111212 AMcs 61C L25 pipeline.6Patterson Spring 99 ©UCBPipelined Laundry: Start work ASAP°Pipelined laundry takes3.5 hours for 4 loads!TaskOrder122 AM6 PM78910111TimeBCDA303030 30303030cs 61C L25 pipeline.7Patterson Spring 99 ©UCBPipelining Lessons° Pipelining doesn’t helplatency of single task, ithelps throughput ofentire workload°Multiple tasksoperatingsimultaneously usingdifferent resources° Potential speedup =Number pipe stages° Time to “fill” pipelineand time to “drain” itreduces speedup:2.3X v. 4X in thisexample6 PM789TimeBCDA303030 303030 30TaskOrdercs 61C L25 pipeline.8Patterson Spring 99 ©UCBPipelining Lessons° Suppose newWasher takes 20minutes, newStasher takes 20minutes. How muchfaster is pipeline?° Pipeline rate limitedby slowest pipelinestage° Unbalanced lengthsof pipe stages alsoreduces speedup6 PM789TimeBCDA303030 303030 30TaskOrdercs 61C L25 pipeline.9Patterson Spring 99 ©UCBReview: Steps in Executing MIPS (Lec. 20)1) Ifetch: Fetch Instruction, Increment PC2) Decode Instruction, Read Registers3) Execute: Mem-ref: Calculate Address Arith-log: Perform Operation Branch: Compare if operands ==4) Memory: Load: Read Data from Memory Store: Write Data to Memory Branch: if operands ==, Change PC5) Write Back: Write Data to Registercs 61C L25 pipeline.10Patterson Spring 99 ©UCBPipelined Execution Representation°Every instruction takes same numberof steps, also called pipeline “stages”IFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBProgram FlowTimecs 61C L25 pipeline.11Patterson Spring 99 ©UCBReview: A Datapath for MIPS (Lec. 20)DataCachePCRegisters ALUInstructionCacheStage 1 Stage 2 Stage 3 (Stage 4)Stage 5IFtch Dcd Exec Mem WB°Use data path figure to represent pipelineALU I$Reg D$ Regcs 61C L25 pipeline.12Patterson Spring 99 ©UCBALU I$Reg D$ Reg I$Graphical Pipeline RepresentationInstr.OrderTime (clock cycles)LoadAddStoreSubOrALU I$Reg D$ RegALU I$Reg D$ RegALUReg D$ RegALU I$Reg D$ Reg(right half highlight means read, left half write)cs 61C L25 pipeline.13Patterson Spring 99 ©UCBExample°Suppose 2 ns for memory access, 2 nsfor ALU operation, and 1 ns for registerfile read or write°Nonpipelined Execution:• lw : IF + Read Reg + ALU + Memory + WriteReg = 2 + 1 + 2 + 2 + 1 = 8 ns• add: IF + Read Reg + ALU + Write Reg= 2 + 1 + 2 + 1 = 6 ns°Pipelined Execution:• Max(IF,Read Reg,ALU, Memory,Write Reg)= 2 nscs 61C L25 pipeline.14Patterson Spring 99 ©UCBAdministrivia°Project 6 (last): Due Today°Next Readings: 7.5°11th homework (last): Due Friday 4/30 7PM• Exercises 2.6, 2.13, 6.1, 6.3, 6.4cs 61C L25 pipeline.15Patterson Spring 99 ©UCBAdministrivia: Rest of 61CF 4/30 Review: Caches/TLB/VM; Section 7.5M 5/3 Deadline to correct your grade recordW 5/5 Review: Interrupts / Polling; A.7F 5/7 61C Summary / Your Cal heritage /HKN Course Evalution (Due: Final 61C Survey in lab; Return)Sun 5/9 Final Review starting 2PM (1 Pimintel)W 5/12 Final (5PM 1 Pimintel)• Need Alternative Final? Contact mds@corycs 61C L25 pipeline.16Patterson Spring 99 ©UCB“What’s This Stuff (Potentially) Bad For?”Linking Entertainment to Violence 100s of studies in recentdecades have revealed a direct correlation between exposure to mediaviolence--including video games--and increased aggression.•"We are reaching that stage of desensitization at which the inflictingof pain and suffering has become a source of entertainment; vicariouspleasure rather than revulsion. We are learning to kill, and we arelearning to like it." Like the tobacco industry, “the evidence is there."• The 14-year-old boy who opened fire on a prayer group in a Ky.school foyer in 1997 was a video-game expert. He had never fired apistol before, but in the ensuing melee, he fired 8 shots, hit 8 people,and killed 3. The average law enforcement officer in the UnitedStates, at a distance of 7 yards, hits fewer than 1 in 5 shots.• Because of freedom of speech is a value that we don't want tocompromise, “it really comes down to the people creating thesegames. That's where the responsibility lies."N.Y. Times, 4/26/99cs 61C L25 pipeline.17Patterson Spring 99 ©UCBPipeline Hazard: Matching socks in later loadA depends on D; stall since folder tied upTaskOrder122 AM6 PM78910111TimeBCDAEFbubble303030 30303030cs 61C L25 pipeline.18Patterson Spring 99 ©UCBProblems for Computers°Limits to pipelining: Hazards preventnext instruction from executing duringits designated clock cycle• Structural hazards: HW cannot supportthis combination of instructions (singleperson to fold and put clothes away)•Control hazards: Pipelining of branches &other instructions stall the pipeline untilthe hazard “bubbles” in the pipeline•Data hazards: Instruction depends onresult of prior instruction still in thepipeline (missing sock)cs 61C L25 pipeline.19Patterson Spring 99 ©UCB I$Single Memory is a Structural HazardLoadInstr 1Instr 2Instr 3Instr 4ALU I$Reg D$ RegALU I$Reg D$ RegALU I$Reg D$ RegALUReg D$ RegALU I$Reg
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