inst eecs berkeley edu cs61c CS61C Machine Structures Example Representing 1 3 in MIPS 1 3 0 33333 10 Lecture 16 Floating Point II 0 25 0 0625 0 015625 0 00390625 2004 10 06 1 4 1 16 1 64 1 256 Lecturer NSOE Steven Kusalo 2 2 2 4 2 6 2 8 0 0101010101 2 20 1 0101010101 2 2 2 Sign 0 20 years from now 1 We ll all have robot servants or 2 The world will be a smoking ruin CS 61C L16 Floating Point II 1 Exponent 2 127 125 01111101 Significand 0101010101 0 0111 1101 0101 0101 0101 0101 0101 010 Kusalo Spring 2005 UCB Representation for In FP divide by 0 should produce not overflow Why OK to do further computations with E g X 0 Y may be a valid comparison Ask math majors IEEE 754 represents Most positive exponent reserved for Significands all zeroes Kusalo Spring 2005 UCB CS 61C L16 Floating Point II 1 Special Numbers What have we defined so far Single Precision Exponent Significand Object 0 0 0 0 nonzero 1 254 anything fl pt 255 0 255 nonzero Professor Kahan had clever ideas Waste not want not Exp 0 255 Sig 0 CS 61C L16 Floating Point II 1 Kusalo Spring 2005 UCB Representation for Not a Number What is sqrt 4 0 or 0 0 If not an error these shouldn t be either Called Not a Number NaN Representation for Denorms 1 2 Problem There s a gap among representable FP numbers around 0 Smallest representable pos num a 1 0 2 2 126 2 126 Exponent 255 Significand nonzero Second smallest representable pos num b 1 000 1 2 2 126 2 126 2 149 Why is this useful Hope NaNs help with debugging a 0 2 126 They contaminate op NaN X NaN b a 2 149 CS 61C L16 Floating Point II 1 Kusalo Spring 2005 UCB CS 61C L16 Floating Point II 1 Kusalo Spring 2005 UCB CS 61C L16 Floating Point II 1 Gaps b 0 a Normalization and implicit 1 is to blame Kusalo Spring 2005 UCB 1 Representation for Denorms 2 2 Overview Solution Reserve exponents significands We still haven t used Exponent 0 Significand nonzero Denormalized number no leading 1 implicit exponent 126 Smallest representable pos num Exponent 0 0 1 254 255 255 Significand 0 nonzero anything 0 nonzero Object 0 Denorm fl pt NaN a 2 149 Second smallest representable pos num b 2 148 0 Kusalo Spring 2005 UCB CS 61C L16 Floating Point II 1 CS 61C L16 Floating Point II 1 Kusalo Spring 2005 UCB IEEE Four Rounding Modes Rounding Math on real numbers we worry about rounding to fit result in the significant field FP hardware carries 2 extra bits of precision and rounds for proper value Rounding occurs when converting Round towards ALWAYS round up 2 1 3 2 1 2 Round towards ALWAYS round down 1 9 1 1 9 2 Truncate Just drop the last bits round towards 0 Round to nearest even default Normal rounding almost 2 5 2 3 5 4 double to single precision floating point to an integer Like you learned in grade school Insures fairness on calculation Half the time we round up other half down Kusalo Spring 2005 UCB CS 61C L16 Floating Point II 1 CS 61C L16 Floating Point II 1 Kusalo Spring 2005 UCB Integer Multiplication 1 3 Integer Multiplication 2 3 Paper and pencil example unsigned In MIPS we multiply registers so Multiplicand Multiplier 1000 8 x1001 1000 0000 0000 1000 01001000 32 bit value x 32 bit value 64 bit value 9 Syntax of Multiplication signed mult register1 register2 Multiplies 32 bit values in those registers puts 64 bit product in special result regs puts product upper half in hi lower half in lo m bits x n bits m n bit product hi and lo are 2 registers separate from the 32 general purpose registers Use mfhi register mflo register to move from hi lo to another register CS 61C L16 Floating Point II 1 Kusalo Spring 2005 UCB CS 61C L16 Floating Point II 1 Kusalo Spring 2005 UCB 2 Integer Multiplication 3 3 Integer Division 1 2 Example Paper and pencil example unsigned in C a b c in MIPS let b be s2 let c be s3 and let a be s0 and s1 since it may be up to 64 bits mult mfhi of into mflo s2 s3 s0 s0 s1 b c upper half product lower half of product into s1 1001 Quotient Divisor 1000 1001010 Dividend 1000 10 101 1010 1000 10 Remainder or Modulo result Dividend Quotient x Divisor Remainder Note Often we only care about the lower half of the product Kusalo Spring 2005 UCB CS 61C L16 Floating Point II 1 CS 61C L16 Floating Point II 1 Kusalo Spring 2005 UCB Integer Division 2 2 Unsigned Instructions Overflow Syntax of Division signed MIPS also has versions of mult div for unsigned operands multu div register1 register2 Divides 32 bit register 1 by 32 bit register 2 puts remainder of division in hi quotient in lo Implements C division and modulo Example in C a c d b c d in MIPS a s0 b s1 c s2 d s3 div s2 s3 mflo s0 mfhi s1 Up to the software to check hi Kusalo Spring 2005 UCB FP Addition Subtraction CS 61C L16 Floating Point II 1 Kusalo Spring 2005 UCB MIPS Floating Point Architecture Separate floating point instructions Much more difficult than with integers can t just add significands How do we do it De normalize to match larger exponent Add significands to get resulting one Normalize check for under overflow Round if needed may need to renormalize If signs do a subtract Subtract similar If signs for add or for sub what s ans sign Question How do we integrate this into the integer arithmetic unit Answer We don t CS 61C L16 Floating Point II 1 Determines whether or not the product and quotient are changed if the operands are signed or unsigned MIPS does not check overflow on ANY signed unsigned multiply divide instr lo c d hi c d get quotient get remainder CS 61C L16 Floating Point II 1 divu Kusalo Spring 2005 UCB Single Precision add s sub s mul s div s Double Precision add d sub d mul d div d These are far more complicated than their integer counterparts Can take much longer to execute CS 61C L16 Floating Point II 1 Kusalo Spring 2005 UCB 3 MIPS Floating Point Architecture 2 MIPS Floating Point Architecture 3 1990 Solution Make a completely separate chip that handles only FP Problems Coprocessor 1 FP chip Inefficient to have different instructions take vastly differing amounts of time Generally a particular piece of data will not change FP int within a program Only 1 type of instruction will be used on it Some programs do no FP calculations It takes lots of hardware relative to integers to do FP fast contains 32 32 bit registers f0 f1 most …
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