PowerPoint PresentationSlide 2Review…Accumulator ExampleFirst try…Does this work?Second try…How about this?Register Details…What’s in it anyway?What’s the timing of a Flip-flop? (1/2)What’s the timing of a Flip-flop? (2/2)Administrivia - MidtermAccumulator Revisited (proper timing 1/2)Accumulator Revisited (proper timing 2/2)Pipelining to improve performance (1/2)Pipelining to improve performance (2/2)Finite State Machines IntroductionFinite State Machine Example: 3 ones…Hardware Implementation of FSMGeneral Model for Synchronous SystemsPeer Instruction“And In conclusion…”CS61C L21 State Elements: CircuitsThat Remember (1)Garcia © UCBLecturer PSOE Dan Garciawww.cs.berkeley.edu/~ddgarciainst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 21 – State Elements: Circuits That RememberCPU, GPU, now PPU! Ageia’s “PhysX” chip willaccelerate physics common to video games: rigid, soft body & fluid dynamics, collision detection, finite element analysis, hair & clothing sim!www.ageia.com/technology.htmlCS61C L21 State Elements: CircuitsThat Remember (2)Garcia © UCBProf Richard KarpTuring Award Winner, Distinguished Teacherupe.cs.berkeley.eduUPE Undergraduate Lecture SeriesThe First 30 Years of Berkeley CS 3/10 Thursday, 6-7pm 306 Soda A personal perspective on the history of the Computer Science Division, including the personalities and politics benind its formation, its greatest achievements, and its prospects for the future.CS61C L21 State Elements: CircuitsThat Remember (3)Garcia © UCBReview…•ISA is very important abstraction layer•Contract between HW and SW•Basic building blocks are logic gates•Clocks control pulse of our circuits•Voltages are analog, quantized to 0/1•Circuit delays are fact of life•Two types•Stateless Combinational Logic (&,|,~), in which output is function of input only•State circuits (e.g., registers)CS61C L21 State Elements: CircuitsThat Remember (4)Garcia © UCBAccumulator ExampleWant: S=0; for (i=0;i<n;i++) S = S + XiCS61C L21 State Elements: CircuitsThat Remember (5)Garcia © UCBFirst try…Does this work?Nope! Reason #1… What is there to control thenext iteration of the ‘for’ loop?Reason #2… How do we say: ‘S=0’?Feedback!CS61C L21 State Elements: CircuitsThat Remember (6)Garcia © UCBSecond try…How about this?Roughtiming…Yep!CS61C L21 State Elements: CircuitsThat Remember (7)Garcia © UCBRegister Details…What’s in it anyway?•n instances of a “Flip-Flop”, called that because the output flips and flops betw. 0,1 •D is “data”•Q is “output”•Also called “d-q Flip-Flop”,“d-type Flip-Flop”CS61C L21 State Elements: CircuitsThat Remember (8)Garcia © UCBWhat’s the timing of a Flip-flop? (1/2)•Edge-triggered d-type flip-flop•This one is “positive edge-triggered”•“On the rising edge of the clock, the input d is sampled and transferred to the output. At all other times, the input d is ignored.”CS61C L21 State Elements: CircuitsThat Remember (9)Garcia © UCBWhat’s the timing of a Flip-flop? (2/2)•Edge-triggered d-type flip-flop•This one is “positive edge-triggered”•“On the rising edge of the clock, the input d is sampled and transferred to the output. At all other times, the input d is ignored.”CS61C L21 State Elements: CircuitsThat Remember (10)Garcia © UCBAdministrivia - Midterm•Your TAs and readers stayed up until 6:30am to get your exams back to you!•x: 47, Median: 48, : 14.4CS61C L21 State Elements: CircuitsThat Remember (11)Garcia © UCBAccumulator Revisited (proper timing 1/2)CS61C L21 State Elements: CircuitsThat Remember (12)Garcia © UCBAccumulator Revisited (proper timing 2/2)CS61C L21 State Elements: CircuitsThat Remember (13)Garcia © UCBPipelining to improve performance (1/2)Timing…CS61C L21 State Elements: CircuitsThat Remember (14)Garcia © UCBPipelining to improve performance (2/2)Timing…CS61C L21 State Elements: CircuitsThat Remember (15)Garcia © UCBFinite State Machines IntroductionCS61C L21 State Elements: CircuitsThat Remember (16)Garcia © UCBFinite State Machine Example: 3 ones…Draw the FSM…PS Input NS Output00 0 00 000 1 01 001 0 00 001 1 10 010 0 00 010 1 00 1Truth table…CS61C L21 State Elements: CircuitsThat Remember (17)Garcia © UCBHardware Implementation of FSM+= ?CS61C L21 State Elements: CircuitsThat Remember (18)Garcia © UCBGeneral Model for Synchronous SystemsCS61C L21 State Elements: CircuitsThat Remember (19)Garcia © UCBPeer InstructionA. HW feedback akin to SW recursionB. We can implement a D-Q flipflop as simple CL (And, Or, Not gates) C. You can build a FSM to signal when an equal number of 0s and 1s has appeared in the input. ABC1: FFF2: FFT 3: FTF4: FTT5: TFF6: TFT7: TTF8: TTTCS61C L21 State Elements: CircuitsThat Remember (21)Garcia © UCB“And In conclusion…”•We use feedback to maintain state•Register files used to build memories•D-FlipFlops used to build Register files•Clocks tell us when D-FlipFlops change•Setup and Hold times important•We pipeline big-delay CL for faster clock•Finite State Machines extremely useful•You’ll see them in HW classes (150,152) &
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