Berkeley COMPSCI 61C - Other Instruction Sets: HP­PA and Intel x86 (34 pages)

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Other Instruction Sets: HP­PA and Intel x86



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Other Instruction Sets: HP­PA and Intel x86

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Pages:
34
School:
University of California, Berkeley
Course:
Compsci 61c - Machine Structures
Machine Structures Documents
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CS61C Other Instruction Sets HP PA and Intel x86 Lecture 22 April 16 1999 Dave Patterson http cs berkeley edu patterson www inst eecs berkeley edu cs61c schedule html cs 61C L22 x86 1 Patterson Spring 99 UCB Outlin e Review Datapath ALU HP PA vs MIPS Example HP PA vs MIPS Administrivia Computers in the News 80x86 History 80x86 instructions vs MIPS Example 80x86 Conclusion cs 61C L22 x86 2 Patterson Spring 99 UCB Review 1 2 Subtract included to ALU by adding one s complement of B Multiple by shift and add Divide by shift and subtract then restore by add if didn t fit Can Multiply Divide simply by adding 64 bit shift register to ALU MIPS allows multiply divide in parallel with ALU operations cs 61C L22 x86 3 Patterson Spring 99 UCB Review 2 2 1 bit ALU with Subtract Support CarryIn Binvert Op Note And Or Add occur in parallel with multiplexor A 0 selecting the desired result B 0 1 1 2 CarryOut cs 61C L22 x86 4 C Definition Binvert Op C 0 0 A and B 1 0 A and B 0 1 A or B 1 1 A or B 0 1 A B CarryIn 1 1 A B CarryIn Patterson Spring 99 UCB MIPS vs HP PA Address 32 bit 32 bit Page size 4KB 4KB Data aligned Data aligned Regs 0 1 31 r0 r1 r31 Reg 0 0 r0 Return address 31 r2 Destination reg Left Right add rd rs1 rs2 cs 61C L22 x86 5 addo rs1 rs2 rd Patterson Spring 99 UCB Instructions MIPS vs HP PA addu addiu addl addi subu subl subi and or xor and or xor lw ldw load word sw stw store word mov copy li ldi lui ldil load imm left cs 61C L22 x86 6 Patterson Spring 99 UCB Branch MIPS vs HP PA beq cmpb compare branch bne cmpb less or greater slt beq cmpb slt bne cmpb jal bl L0 r2 branch link into r2 jr 31 bv 0 r2 branch via r2 cs 61C L22 x86 7 Patterson Spring 99 UCB Unique Instructions ldo load offset Calculate address like a load but load address into register not data Load 32 bit constant ldil left const rx ldo right const rx rx cs 61C L22 x86 8 Patterson Spring 99 UCB HP PA data addressing ldw base reg offset like MIPS ldw 4608 0 r19 r25 r19 4608 ldwx base reg index unlike MIPS ldwx r20 0 r19 r25 r19 r20 scaled reg offset unlike MIPS ldw s 12 0 r19 r25 r19 2 12 Purpose to turn index into byte address ldw s shifts left reg by 0 1 2 3 for byte halfword word doubleword data transfer scaled reg index ldwx s cs 61C L22 x86 9 Patterson Spring 99 UCB HP PA data addressing Cont d Update register with calculated address as part of instruction autoupdate ldw 4608 1 r19 r25 r25 Mem r19 4608 r19 r19 4608 ldwx r20 1 r19 r25 r25 Mem r19 d20 r19 r19 r20 ldw s 8 1 r2 r4 r4 Mem r2 2 8 r2 r2 2 8 ldwx s r3 1 r2 r4 r4 Mem r2 2 r3 r2 r2 2 r3 Purpose fewer instructions performance cs 61C L22 x86 10 Patterson Spring 99 UCB While in C Assembly MIPS C while save i k i i j i j k s3 s4 s5 addi s6 sp 504 save Loop sll t0 s3 2 t0 4 i M add t0 t0 s6 t0 Addr I lw t1 0 t0 t1 save i P bne t1 s5 Exit goto Exit if save i k S add s3 s3 s4 i i j j Loop goto Loop Exit cs 61C L22 x86 11 Patterson Spring 99 UCB While in C Assembly HP PA C while save i k i i j i j k r3 r4 r5 ldo 504 r30 r7 save Loop ldwx s r3 0 r7 r6 save i H comb r5 r6 Exit P addl r3 r4 r3 i i j P b Loop goto Loop A Exit Note ldwx s replaces sll add lw in loop cs 61C L22 x86 12 Patterson Spring 99 UCB HP PA Unique Instructions Shift Left zdep rs pos len rd deposit right adjusted field of width len to bit pos and zero rest of register MIPS sll rd 2 rs zdep rs 31 2 32 2 rd zdep rs 29 30 rd zvdep rs len rd deposit right adjusted of width len to bit specified in reg sar and zero rest MIPS sllv rd rv rs mtsar rv zvdep rs 32 rd extr vextr is opposite extracts cs 61C L22 x86 13 Patterson Spring 99 UCB HP PA Unique Instructions extru rs pos len rd extract field of width len at bit pos place right adjusted into register and zero rest extrs sign extends vextrs uses sar MIPS srl rd 2 rs extru rs 31 2 32 2 rd extru rs 29 30 rd Shift left 1 2 or 3 bits and add Purpose provide a primitive operations for multiply so that can multiply by constants more efficiently MIPS sll rx 2 rs add rd rx rt sh2addl rs rt rd cs 61C L22 x86 14 Patterson Spring 99 UCB HP PA Floating Point fldws load word into FP reg fsub sgl SP FP subtract fdiv sgl SP FP divide fcnvxf sgl sgl convert int to SP FP fstws store word from FP reg 58 Single Precision floating point registers called fr4L fr4R fr5L fr5R fr30L fr30R fr31L fr31R cs 61C L22 x86 15 Patterson Spring 99 UCB Administrivia Project 6 MIPS sprintf Due Wed April 28 Next Readings 2 1 to 2 5 9th homework Due Today Ex 7 35 4 24 10th homework Due Wednesday 4 21 7PM Exercises 4 43 3 17 assume each instruction takes 1 clock cycle performance no instructions executed clock cycle time ignore CPI comment cs 61C L22 x86 16 Patterson Spring 99 UCB Administrivia Rest of W61C 4 21 Performance Reading sections 2 1 2 5 F 4 23 Review Procedures Variable Args Due x86 HP ISA lab homework 10 W 4 28 Processor Pipelining section 6 1 F 4 30 Review Caches TLB VM section 7 5 Due Project 6 sprintf in MIPS homework 11 M 5 3 Deadline to correct your grade record W 5 5 Review Interrupts Polling F 5 7 61C Summary Your Cal heritage Due Final 61C Survey in lab Sun 5 9 Final Review starting 2PM 1 Pimintel W 5 12 Final 5PM 1 Pimintel Need Alternative Final Contact mds cory cs 61C L22 x86 17 Patterson Spring 99 UCB Computers in the News Age Gains Respect of Computer Economists N Y Times April 14 1999 1990 You can see the Computer Age everywhere but in the productivity statistics Robert Solow a MIT Nobel prizewinner Productivity growth has picked up 2 1995 98 v 1 for 1974 95 apparently having to do with the increased speed efficiency that the Internet and other pervasive information technology advances for mundane businesses operations Greenspan 1999 economy …


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