PowerPoint PresentationReview: Why We Use CachesN-Way Set Associative Cache (1/4)N-Way Set Associative Cache (2/4)N-Way Set Associative Cache (3/4)N-Way Set Associative Cache (4/4)Associative Cache ExampleSlide 8Block Replacement Policy (1/2)Block Replacement Policy (2/2)Block Replacement Policy: LRUBlock Replacement ExampleBlock Replacement Example: LRUBig IdeaExampleAdministriviaWays to reduce miss rateImproving Miss PenaltyAnalyzing Multi-level cache hierarchyTypical ScaleExample: with L2 cacheExample: without L2 cacheWhat to do on a write hit?Generalized CachingAn actual CPU -- Early PowerPCPeer InstructionsPeer Instructions AnswerAnd in Conclusion…CS61C L34 Caches IV (1)Garcia © UCBLecturer PSOE Dan Garciawww.cs.berkeley.edu/~ddgarciainst.eecs.berkeley.edu/~cs61c CS61C : Machine StructuresLecture 34 Caches IVMicrosoft and U Maryland areinvestigating the use of a one-hand (thumb-driven) interface for controlling PDAs and cell phones (normally one needs 2 hands, one to hold the device, one for a stylus). brighthand.com/article/Microsoft_is_All_ThumbsThumb-based interfaces? CS61C L34 Caches IV (2)Garcia © UCBReview: Why We Use CachesµProc60%/yr.DRAM7%/yr.110100100019801981198319841985198619871988198919901991199219931994199519961997199819992000DRAMCPU1982Processor-MemoryPerformance Gap:(grows 50% / year)Performance“Moore’s Law”•1989 first Intel CPU with cache on chip•1998 Pentium III has two levels of cache on chipCS61C L34 Caches IV (3)Garcia © UCBN-Way Set Associative Cache (1/4)•Memory address fields:•Tag: same as before•Offset: same as before•Index: points us to the correct “row” (called a set in this case)•So what’s the difference?•each set contains multiple blocks•once we’ve found correct set, must compare with all tags in that set to find our dataCS61C L34 Caches IV (4)Garcia © UCBN-Way Set Associative Cache (2/4)•Summary:•cache is direct-mapped w/respect to sets•each set is fully associative•basically N direct-mapped caches working in parallel: each has its own valid bit and dataCS61C L34 Caches IV (5)Garcia © UCBN-Way Set Associative Cache (3/4)•Given memory address:•Find correct set using Index value.•Compare Tag with all Tag values in the determined set.•If a match occurs, hit!, otherwise a miss.•Finally, use the offset field as usual to find the desired data within the block.CS61C L34 Caches IV (6)Garcia © UCBN-Way Set Associative Cache (4/4)•What’s so great about this?•even a 2-way set assoc cache avoids a lot of conflict misses•hardware cost isn’t that bad: only need N comparators•In fact, for a cache with M blocks,•it’s Direct-Mapped if it’s 1-way set assoc•it’s Fully Assoc if it’s M-way set assoc•so these two are just special cases of the more general set associative designCS61C L34 Caches IV (7)Garcia © UCBAssociative Cache Example•Recall this is how a simple direct mapped cache looked.•This is also a 1-way set-associative cache!MemoryMemory Address0123456789ABCDEF4 Byte Direct Mapped CacheCache Index0123CS61C L34 Caches IV (8)Garcia © UCBAssociative Cache Example•Here’s a simple 2 way set associative cache.MemoryMemory Address0123456789ABCDEFCache Index0011CS61C L34 Caches IV (9)Garcia © UCBBlock Replacement Policy (1/2)•Direct-Mapped Cache: index completely specifies position which position a block can go in on a miss•N-Way Set Assoc: index specifies a set, but block can occupy any position within the set on a miss•Fully Associative: block can be written into any position•Question: if we have the choice, where should we write an incoming block?CS61C L34 Caches IV (10)Garcia © UCBBlock Replacement Policy (2/2)•If there are any locations with valid bit off (empty), then usually write the new block into the first one.•If all possible locations already have a valid block, we must pick a replacement policy: rule by which we determine which block gets “cached out” on a miss.CS61C L34 Caches IV (11)Garcia © UCBBlock Replacement Policy: LRU•LRU (Least Recently Used)•Idea: cache out block which has been accessed (read or write) least recently•Pro: temporal locality recent past use implies likely future use: in fact, this is a very effective policy•Con: with 2-way set assoc, easy to keep track (one LRU bit); with 4-way or greater, requires complicated hardware and much time to keep track of thisCS61C L34 Caches IV (12)Garcia © UCBBlock Replacement Example•We have a 2-way set associative cache with a four word total capacity and one word blocks. We perform the following word accesses (ignore bytes for this problem):0, 2, 0, 1, 4, 0, 2, 3, 5, 4How many hits and how many misses will there be for the LRU block replacement policy?CS61C L34 Caches IV (13)Garcia © UCBBlock Replacement Example: LRU•Addresses 0, 2, 0, 1, 4, 0, ...0lru21lruloc 0 loc 1set 0set 10 2lruset 0set 1 0: miss, bring into set 0 (loc 0) 2: miss, bring into set 0 (loc 1) 0: hit 1: miss, bring into set 1 (loc 0) 4: miss, bring into set 0 (loc 1, replace 2) 0: hit0set 0set 1lrulru0 2set 0set 1lrulruset 0set 101lrulru24lruset 0set 10 41lrulrulruCS61C L34 Caches IV (14)Garcia © UCBBig Idea•How to choose between associativity, block size, replacement policy?•Design against a performance model•Minimize: Average Memory Access Time = Hit Time + Miss Penalty x Miss Rate•influenced by technology & program behavior•Note: Hit Time encompasses Hit Rate!!!•Create the illusion of a memory that is large, cheap, and fast - on averageCS61C L34 Caches IV (15)Garcia © UCBExample•Assume •Hit Time = 1 cycle•Miss rate = 5%•Miss penalty = 20 cycles•Calculate AMAT…•Avg mem access time = 1 + 0.05 x 20= 1 + 1 cycles= 2 cyclesCS61C L34 Caches IV (16)Garcia © UCBAdministrivia•Do your reading! VM is coming up, and it’s shown to be hard for students!•Project 3 out today, due Next WedCS61C L34 Caches IV (17)Garcia © UCBWays to reduce miss rate•Larger cache•limited by cost and technology•hit time of first level cache < cycle time•More places in the cache to put each block of memory – associativity•fully-associative-any block any line•N-way set associated-N places for each block-direct map: N=1CS61C L34 Caches IV (18)Garcia © UCBImproving Miss Penalty•When caches first became popular, Miss Penalty ~ 10 processor clock cycles•Today 2400 MHz Processor (0.4 ns per clock cycle) and 80 ns to go to DRAM 200 processor clock
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