CS 61C L06 MIPS Intro (1)A Carle, Summer 2005 © UCBinst.eecs.berkeley.edu/~cs61c/su05CS61C : Machine StructuresLecture #6: Intro to MIPS2005-06-28Andy CarleCS 61C L06 MIPS Intro (2)A Carle, Summer 2005 © UCBReview•Several techniques for managing heap w/ malloc/free: best-, first-, next-fit, slab,buddy• 2 types of memory fragmentation: internal & external; all suffer from some kind of frag.• Each technique has strengths and weaknesses, none is definitively best•Automatic memory management relieves programmer from managing memory.• All require help from language and compiler• Reference Count: not for circular structures• Mark and Sweep: complicated and slow, works• Copying: move active objects back and forthCS 61C L06 MIPS Intro (3)A Carle, Summer 2005 © UCBBuddy System Review•Legend: FREE ALLOCATED SPLIT128: 064: 0032: 001016: 00000010000 001 010 011 100 101 110 111Initial State Î Free(001) Î Free(000) Î Free(111) Î Malloc(16)1Kudos to Kurt Meinz for these fine slidesCS 61C L06 MIPS Intro (4)A Carle, Summer 2005 © UCBBuddy System•Legend: FREE ALLOCATED SPLIT128: 064: 0032: 001016: 01000010000 001 010 011 100 101 110 111Initial State Î Free(001) Î Free(000) Î Free(111) Î Malloc(16)1CS 61C L06 MIPS Intro (5)A Carle, Summer 2005 © UCBBuddy System•Legend: FREE ALLOCATED SPLIT128: 064: 0032: 001016: 11000010000 001 010 011 100 101 110 111Initial State Î Free(001) Î Free(000) Î Free(111) Î Malloc(16)1CS 61C L06 MIPS Intro (6)A Carle, Summer 2005 © UCBBuddy System•Legend: FREE ALLOCATED SPLIT128: 064: 0032: 101016: 00000010000 001 010 011 100 101 110 111Initial State Î Free(001) Î Free(000) Î Free(111) Î Malloc(16)2CS 61C L06 MIPS Intro (7)A Carle, Summer 2005 © UCBBuddy System•Legend: FREE ALLOCATED SPLIT128: 064: 0032: 101016: 00000011000 001 010 011 100 101 110 111Initial State Î Free(001) Î Free(000) Î Free(111) Î Malloc(16)1CS 61C L06 MIPS Intro (8)A Carle, Summer 2005 © UCBBuddy System•Legend: FREE ALLOCATED SPLIT128: 064: 0032: 101116: 00000000000 001 010 011 100 101 110 111Initial State Î Free(001) Î Free(000) Î Free(111) Î Malloc(16)2CS 61C L06 MIPS Intro (9)A Carle, Summer 2005 © UCBBuddy System•Legend: FREE ALLOCATED SPLIT128: 064: 0132: 100016: 00000000000 001 010 011 100 101 110 111Initial State Î Free(001) Î Free(000) Î Free(111) Î Malloc(16)3CS 61C L06 MIPS Intro (10)A Carle, Summer 2005 © UCBBuddy System•Legend: FREE ALLOCATED SPLIT128: 064: 0132: 000016: 11000000000 001 010 011 100 101 110 111Initial State Î Free(001) Î Free(000) Î Free(111) Î Malloc(16)1CS 61C L06 MIPS Intro (11)A Carle, Summer 2005 © UCBBuddy System•Legend: FREE ALLOCATED SPLIT128: 064: 0132: 000016: 01000000000 001 010 011 100 101 110 111Initial State Î Free(001) Î Free(000) Î Free(111) Î Malloc(16)2CS 61C L06 MIPS Intro (12)A Carle, Summer 2005 © UCBNew Topic!MIPS Assembly LanguageCS 61C L06 MIPS Intro (13)A Carle, Summer 2005 © UCBAssembly Language•Basic job of a CPU: execute lots of instructions.•Instructions are the primitive operations that the CPU may execute.•Different CPUs implement different sets of instructions. The set of instructions a particular CPU implements is an Instruction Set Architecture (ISA).• Examples: Intel 80x86 (Pentium 4), IBM/Motorola PowerPC (Macintosh), MIPS, Intel IA64, ...CS 61C L06 MIPS Intro (14)A Carle, Summer 2005 © UCBInstruction Set Architectures•Early trend was to add more and more instructions to new CPUs to do elaborate operations• VAX architecture had an instruction to multiply polynomials!•RISC philosophy (Cocke IBM, Patterson, Hennessy, 1980s) –Reduced Instruction Set Computing• Keep the instruction set small and simple, makes it easier to build fast hardware.• Let software do complicated operations by composing simpler ones.CS 61C L06 MIPS Intro (15)A Carle, Summer 2005 © UCBISA Design•Must Run Fast In Hardware ÎEliminate sources of complexity.• Symbolic Lookup Î fixed var names/#• Strong typing Î No Typing• Nested expressions Î Fixed format Inst• Many operators Î small set of instsSoftwareHardwareCS 61C L06 MIPS Intro (16)A Carle, Summer 2005 © UCBMIPS Architecture•MIPS – semiconductor company that built one of the first commercial RISC architectures•We will study the MIPS architecture in some detail in this class (also used in upper division courses CS 152, 162, 164)•Why MIPS instead of Intel 80x86?• MIPS is simple, elegant. Don’t want to get bogged down in gritty details.• MIPS widely used in embedded apps, x86 little used in embedded, and more embedded computers than PCsCS 61C L06 MIPS Intro (17)A Carle, Summer 2005 © UCBAssembly Variables: Registers (1/4)•Unlike HLL like C or Java, assembly cannot use variables• Why not? Keep Hardware Simple•Assembly Operands are registers• limited number of special locations built directly into the hardware• operations can only be performed on these!•Benefit: Since registers are directly in hardware, they are very fast (faster than 1 billionth of a second)CS 61C L06 MIPS Intro (18)A Carle, Summer 2005 © UCBAssembly Variables: Registers (2/4)•Drawback: Since registers are in hardware, there are a predetermined number of them• Solution: MIPS code must be very carefully put together to efficiently use registers•32 registers in MIPS• Why just 32? Smaller is faster•Each MIPS register is 32 bits wide• Groups of 32 bits called a word in MIPSCS 61C L06 MIPS Intro (19)A Carle, Summer 2005 © UCBAssembly Variables: Registers (3/4)•Registers are numbered from 0 to 31•Each register can be referred to by number or name•Number references:$0, $1, $2, … $30, $31CS 61C L06 MIPS Intro (20)A Carle, Summer 2005 © UCBAssembly Variables: Registers (4/4)•By convention, each register also has a name to make it easier to code•For now:$16 - $23 Î $s0 - $s7(correspond to C variables)$8 - $15 Î $t0 - $t7(correspond to temporary variables)Later will explain other 16 register names•In general, use names to make your code more readableCS 61C L06 MIPS Intro (21)A Carle, Summer 2005 © UCBC, Java variables vs. registers•In C (and most High Level Languages) variables declared first and given a type• Example: int fahr, celsius; char a, b, c, d, e;•Each
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