inst.eecs.berkeley.edu/~cs61c !UCB CS61C : Machine Structures Lecture 25 CPU design (of a single-cycle CPU) 2010-03-29 Intel is prototyping circuits that operate at low voltages to save power, and if/when errors occur, backing up and restarting the calculation at a higher voltage… Lecturer SOE Dan Garcia technologyreview.com/computing/24843/ Hello to Valon Mehmeti from Macedonia!CS61C L25 CPU Design : Designing a Single-Cycle CPU (2) Garcia, Spring 2010 © UCB Review CPU design involves Datapath, Control Datapath in MIPS involves 5 CPU stages 1. Instruction Fetch 2. Instruction Decode & Register Read 3. ALU (Execute) 4. Memory 5. Register WriteCS61C L25 CPU Design : Designing a Single-Cycle CPU (3) Garcia, Spring 2010 © UCB Datapath Summary The datapath based on data transfers required to perform instructions A controller causes the right transfers to happen PC"instruction"memory"+4"rt"rs"rd"registers"Data"memory"imm"ALU!Controller"opcode, funct"CS61C L25 CPU Design : Designing a Single-Cycle CPU (4) Garcia, Spring 2010 © UCB How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) ⇒ datapath requirements 1. meaning of each instruction is given by the register transfers 2. datapath must include storage element for ISA registers 3. datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logicCS61C L25 CPU Design : Designing a Single-Cycle CPU (5) Garcia, Spring 2010 © UCB All MIPS instructions are 32 bits long. 3 formats: R-type I-type J-type The different fields are: op: operation (“opcode”) of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of jump instruction op! target address!0!26!31!6 bits! 26 bits!op! rs! rt! rd! shamt! funct!0!6!11!16!21!26!31!6 bits! 6 bits!5 bits!5 bits!5 bits!5 bits!op! rs! rt!address/immediate!0!16!21!26!31!6 bits! 16 bits!5 bits!5 bits!Review: The MIPS Instruction FormatsCS61C L25 CPU Design : Designing a Single-Cycle CPU (6) Garcia, Spring 2010 © UCB ADDU and SUBU addu rd,rs,rt subu rd,rs,rt OR Immediate: ori rt,rs,imm16 LOAD and STORE Word lw rt,rs,imm16 sw rt,rs,imm16 BRANCH: beq rs,rt,imm16 op! rs! rt! rd! shamt! funct!0!6!11!16!21!26!31!6 bits! 6 bits!5 bits!5 bits!5 bits!5 bits!op! rs! rt! immediate!0!16!21!26!31!6 bits! 16 bits!5 bits!5 bits!op! rs! rt! immediate!0!16!21!26!31!6 bits! 16 bits!5 bits!5 bits!op! rs! rt! immediate!0!16!21!26!31!6 bits! 16 bits!5 bits!5 bits!Step 1a: The MIPS-lite Subset for todayCS61C L25 CPU Design : Designing a Single-Cycle CPU (7) Garcia, Spring 2010 © UCB RTL gives the meaning of the instructions All start by fetching the instruction {op , rs , rt , rd , shamt , funct} ← MEM[ PC ]!{op , rs , rt , Imm16} ← MEM[ PC ]!inst !Register Transfers!ADDU !R[rd] ← R[rs] + R[rt]; !PC ← PC + 4!SUBU !R[rd] ← R[rs] – R[rt]; !PC ← PC + 4!ORI !R[rt] ← R[rs] | zero_ext(Imm16); !PC ← PC + 4!LOAD !R[rt] ← MEM[ R[rs] + sign_ext(Imm16)]; PC ← PC + 4!STORE !MEM[ R[rs] + sign_ext(Imm16) ] ← R[rt]; PC ← PC + 4!BEQ if ( R[rs] == R[rt] ) then " PC ← PC + 4 + (sign_ext(Imm16) || 00)" else PC ← PC + 4!Register Transfer Language (RTL)CS61C L25 CPU Design : Designing a Single-Cycle CPU (8) Garcia, Spring 2010 © UCB Step 1: Requirements of the Instruction Set Memory (MEM) instructions & data (will use one for each) Registers (R: 32 x 32) read RS read RT Write RT or RD PC Extender (sign/zero extend) Add/Sub/OR unit for operation on register(s) or extended immediate Add 4 (+ maybe extended immediate) to PC Compare registers?CS61C L25 CPU Design : Designing a Single-Cycle CPU (9) Garcia, Spring 2010 © UCB Step 2: Components of the Datapath Combinational Elements Storage Elements Clocking methodologyCS61C L25 CPU Design : Designing a Single-Cycle CPU (10) Garcia, Spring 2010 © UCB Combinational Logic Elements (Building Blocks) Adder MUX ALU 32!32!A!B!32!Sum!CarryOut!32!32!A!B!32!Result!OP!32!A!B!32!Y!32!Select!Adder!MUX!ALU!CarryIn!CS61C L25 CPU Design : Designing a Single-Cycle CPU (11) Garcia, Spring 2010 © UCB ALU Needs for MIPS-lite + Rest of MIPS Addition, subtraction, logical OR, ==: ADDU R[rd] = R[rs] + R[rt]; ... SUBU R[rd] = R[rs] – R[rt]; ... ORI R[rt] = R[rs] | zero_ext(Imm16)... BEQ if ( R[rs] == R[rt] )... Test to see if output == 0 for any ALU operation gives == test. How? P&H also adds AND, Set Less Than (1 if A < B, 0 otherwise) ALU follows chap 5CS61C L25 CPU Design : Designing a Single-Cycle CPU (12) Garcia, Spring 2010 © UCB Administrivia Administrivia?CS61C L25 CPU Design : Designing a Single-Cycle CPU (13) Garcia, Spring 2010 © UCB What Hardware Is Needed? (1/2) PC: a register which keeps track of memory addr of the next instruction General Purpose Registers used in Stages 2 (Read) and 5 (Write) MIPS has 32 of these Memory used in Stages 1 (Fetch) and 4 (R/W) cache system makes these two stages as fast as the others, on averageCS61C L25 CPU Design : Designing a Single-Cycle CPU (14) Garcia, Spring 2010 © UCB What Hardware Is Needed? (2/2) ALU used in Stage 3 something that performs all necessary functions: arithmetic, logicals, etc. we’ll design details later Miscellaneous Registers In implementations with only one stage per clock cycle, registers are inserted between stages to hold intermediate data and control signals as they travels from stage to stage. Note: Register is a general purpose term meaning something that stores bits. Not all registers are in the “register file”.CS61C L25 CPU Design : Designing a Single-Cycle CPU (15) Garcia, Spring 2010 © UCB Storage Element:
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