inst eecs berkeley edu cs61c UCB CS61C Machine Structures Lecture 25 CPU design of a single cycle CPU Lecturer SOE Dan Garcia 2010 03 29 Hello to Valon Mehmeti from Macedonia Intel is prototyping circuits that operate at low voltages to save power and if when errors occur backing up and restarting the calculation at a higher voltage technologyreview com computing 24843 Review CPU design involves Datapath Control Datapath in MIPS involves 5 CPU stages 1 Instruction Fetch 2 Instruction Decode Register Read 3 ALU Execute 4 Memory 5 Register Write CS61C L25 CPU Design Designing a Single Cycle CPU 2 Garcia Spring 2010 UCB Datapath Summary The datapath based on data transfers 4 ALU Data memory rd rs rt registers PC instruction memory required to perform instructions A controller causes the right transfers to happen imm opcode funct Controller CS61C L25 CPU Design Designing a Single Cycle CPU 3 Garcia Spring 2010 UCB How to Design a Processor step by step 1 Analyze instruction set architecture ISA datapath requirements meaning of each instruction is given by the register transfers 2 datapath must include storage element for ISA registers 3 datapath must support each register transfer 1 2 Select set of datapath components and establish clocking methodology 3 Assemble datapath meeting requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic CS61C L25 CPU Design Designing a Single Cycle CPU 4 Garcia Spring 2010 UCB Review The MIPS Instruction Formats All MIPS instructions are 32 bits long 3 formats R type I type J type 31 26 21 16 op 6 bits 31 26 op 6 bits 31 26 op 6 bits rs 5 bits 21 rs 5 bits rt 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits 0 funct 6 bits 0 address immediate 16 bits 0 target address 26 bits The different fields are op operation opcode of the instruction rs rt rd the source and destination register specifiers shamt shift amount funct selects the variant of the operation in the op field address immediate address offset or immediate value target address target address of jump instruction CS61C L25 CPU Design Designing a Single Cycle CPU 5 Garcia Spring 2010 UCB Step 1a The MIPS lite Subset for today ADDU and SUBU 31 op 6 bits addu rd rs rt subu rd rs rt OR Immediate 31 ori rt rs imm16 LOAD and 31 STORE Word BRANCH 26 op 6 bits 26 op 6 bits lw rt rs imm16 sw rt rs imm16 26 31 beq rs rt imm16 26 op 6 bits CS61C L25 CPU Design Designing a Single Cycle CPU 6 21 rs 5 bits 21 rs 5 bits 21 rs 5 bits 21 rs 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits 16 rt 5 bits immediate 16 bits 0 immediate 16 bits 16 rt 5 bits funct 6 bits 0 16 rt 5 bits 0 0 immediate 16 bits Garcia Spring 2010 UCB Register Transfer Language RTL RTL gives the meaning of the instructions op rs rt rd shamt funct MEM PC op rs rt Imm16 MEM PC All start by fetching the instruction inst Register Transfers ADDU R rd R rs R rt PC PC 4 SUBU R rd R rs R rt PC PC 4 ORI R rt R rs zero ext Imm16 PC PC 4 LOAD R rt MEM R rs sign ext Imm16 PC PC 4 STORE MEM R rs sign ext Imm16 R rt PC PC 4 BEQ if R rs R rt then PC PC 4 sign ext Imm16 00 else PC PC 4 CS61C L25 CPU Design Designing a Single Cycle CPU 7 Garcia Spring 2010 UCB Step 1 Requirements of the Instruction Set Memory MEM instructions data will use one for each Registers R 32 x 32 read RS read RT Write RT or RD PC Extender sign zero extend Add Sub OR unit for operation on register s or extended immediate Add 4 maybe extended immediate to PC Compare registers CS61C L25 CPU Design Designing a Single Cycle CPU 8 Garcia Spring 2010 UCB Step 2 Components of the Datapath Combinational Elements Storage Elements Clocking methodology CS61C L25 CPU Design Designing a Single Cycle CPU 9 Garcia Spring 2010 UCB Combinational Logic Elements Building Blocks Adder CarryIn A B MUX Adder 32 Sum 32 CarryOut 32 Select B 32 MUX A 32 Y 32 OP B 32 ALU ALU A 32 Result 32 CS61C L25 CPU Design Designing a Single Cycle CPU 10 Garcia Spring 2010 UCB ALU Needs for MIPS lite Rest of MIPS Addition subtraction logical OR ADDU R rd R rs R rt SUBU R rd R rs R rt ORI R rt R rs zero ext Imm16 BEQ if R rs R rt Test to see if output 0 for any ALU operation gives test How P H also adds AND Set Less Than 1 if A B 0 otherwise ALU follows chap 5 CS61C L25 CPU Design Designing a Single Cycle CPU 11 Garcia Spring 2010 UCB Administrivia Administrivia CS61C L25 CPU Design Designing a Single Cycle CPU 12 Garcia Spring 2010 UCB What Hardware Is Needed 1 2 PC a register which keeps track of memory addr of the next instruction General Purpose Registers used in Stages 2 Read and 5 Write MIPS has 32 of these Memory used in Stages 1 Fetch and 4 R W cache system makes these two stages as fast as the others on average CS61C L25 CPU Design Designing a Single Cycle CPU 13 Garcia Spring 2010 UCB What Hardware Is Needed 2 2 ALU used in Stage 3 something that performs all necessary functions arithmetic logicals etc we ll design details later Miscellaneous Registers In implementations with only one stage per clock cycle registers are inserted between stages to hold intermediate data and control signals as they travels from stage to stage Note Register is a general purpose term meaning something that stores bits Not all registers are in the register file CS61C L25 CPU Design Designing a Single Cycle CPU 14 Garcia Spring 2010 UCB Storage Element Idealized Memory Memory idealized One input bus Data In One output bus Data Out Memory word is found by Write Enable Address Data In 32 Clk DataOut 32 Address selects the word to put on Data Out Write Enable 1 address selects the memory word to be written via the Data In bus Clock input CLK The CLK input is a factor ONLY during write operation During read operation behaves as a combinational logic block Address valid Data Out valid after access time CS61C L25 CPU Design Designing a Single Cycle CPU 15 Garcia Spring 2010 UCB Storage Element Register Building Block Similar to D Flip Flop except N bit input and output Write Enable input Write Enable Write Enable Data In N Data Out N negated or deasserted 0 Data Out will not change clk asserted 1 Data Out will become Data In on positive edge of clock CS61C L25 CPU Design Designing a Single Cycle CPU 16 …
View Full Document
Unlocking...