inst eecs berkeley edu cs61c UCB CS61C Machine Structures Lecturer SOE Dan Garcia Lecture 13 MIPS Instruction Representation I 2008 02 22 AFTER MOORE S LAW The National Science Foundation NSF requested 20 million to start the Science and Engineering Beyond Moore s Law effort to fund academic research in carbon nanotubes quantum computing massively multicore computers etc that could improve and replace www pcworld com article id 142561 page 1 article html current transistor technology That s Review Register Conventions Each register has a purpose and limits to its usage Learn these and follow them even if you re writing all the code yourself Logical and Shift Instructions Operate on bits individually unlike arithmetic which operate on entire word Use to isolate fields either by masking or by shifting back and forth Use shift left logical sll for multiplication by powers of 2 Use shift right arithmetic sra for division by powers of 2 New Instructions and andi or ori sll srl sra CS61C L12 MIPS Instruction Representation I 2 Garcia Spring 2008 UC 61C Levels of Representation abstractions High Level Language temp v k Program e g C v k v k 1 v k 1 temp Compiler Assembly Language Program e g MIPS Assembler Machine Language Program MIPS Machine Interpretation lw lw sw sw 0000 1010 1100 0101 Hardware Architecture Description e g block diagrams Architecture Implementation t0 t1 t1 t0 1001 1111 0110 1000 0 s2 4 s2 0 s2 4 s2 1100 0101 1010 0000 0110 1000 1111 1001 1010 0000 0101 1100 1111 1001 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111 Register File AL U Logic Circuit Description Circuit Schematic Diagrams CS61C L12 MIPS Instruction Representation I 3 Garcia Spring 2008 UC Overview Instruction Representation Big idea stored program consequences of stored program Instructions as numbers Instruction encoding MIPS instruction format for Add instructions MIPS instruction format for Immediate Data transfer instructions CS61C L12 MIPS Instruction Representation I 4 Garcia Spring 2008 UC Big Idea Stored Program Concept Computers built on 2 key principles Instructions are represented as bit patterns can think of these as numbers Therefore entire programs can be stored in memory to be read or written just like data Simplifies SW HW of computer systems Memory technology for data also used for programs CS61C L12 MIPS Instruction Representation I 5 Garcia Spring 2008 UC Consequence 1 Everything Addressed Since all instructions and data are stored in memory everything has a memory address instructions data words both branches and jumps use these C pointers are just memory addresses they can point to anything in memory Unconstrained use of addresses can lead to nasty bugs up to you in C limits in Java One register keeps address of instruction being executed Program CS61C L12 MIPS Instruction Representation I 6 Garcia Spring 2008 UC Consequence 2 Binary Compatibility Programs are distributed in binary form Programs bound to specific instruction set Different version for Macintoshes and PCs New machines want to run old programs binaries as well as programs compiled to new instructions Leads to backward compatible instruction set evolving over time Selection of Intel 8086 in 1981 for 1st CS61C L12 MIPS Instruction Representation I 7 Garcia Spring 2008 UC Instructions as Numbers 1 2 Currently all data we work with is in words 32 bit blocks Each register is a word lw and sw both access memory one word at a time So how do we represent instructions Remember Computer only understands 1s and 0s so add t0 0 0 is meaningless MIPS wants simplicity since data is in words make instructions be words too CS61C L12 MIPS Instruction Representation I 8 Garcia Spring 2008 UC Instructions as Numbers 2 2 One word is 32 bits so divide instruction word into fields Each field tells processor something about instruction We could define different fields for each instruction but MIPS is based on simplicity so define 3 basic types of instruction formats R format I format J format CS61C L12 MIPS Instruction Representation I 9 Garcia Spring 2008 UC Instruction Formats I format used for instructions with immediates lw and sw since offset counts as an immediate and branches beq and bne but not the shift instructions later J format used for j and jal R format used for all other instructions It will soon become clear why the instructions have been partitioned in this way CS61C L12 MIPS Instruction Representation I 10 Garcia Spring 2008 UC R Format Instructions 1 5 Define fields of the following number of bits each 6 5 5 5 5 6 32 6 5 5 5 5 6 opcode For simplicity has afunct rs rteachrdfield shamt name Important On these slides and in book each field is viewed as a 5 or 6 bit unsigned integer not as part of a 32 bit integer Consequence 5 bit fields can represent Garcia Spring 2008 UC CS61C L12 MIPS Instruction Representation I 11 R Format Instructions 2 5 What do these field integer values tell us opcode partially specifies what instruction it is Note This number is equal to 0 for all RFormat instructions funct combined with opcode this number exactly specifies the instruction Question Why aren t opcode and funct a single 12 bit field We ll answer this later CS61C L12 MIPS Instruction Representation I 12 Garcia Spring 2008 UC R Format Instructions 3 5 More fields rs Source Register generally used to specify register containing first operand rt Target Register generally used to specify register containing second operand note that name is misleading rd Destination Register generally used to specify register which will receive result of computation CS61C L12 MIPS Instruction Representation I 13 Garcia Spring 2008 UC R Format Instructions 4 5 Notes about register fields Each register field is exactly 5 bits which means that it can specify any unsigned integer in the range 0 31 Each of these fields specifies one of the 32 registers by number The word generally was used because there are exceptions that we ll see later E g mult and div have nothing important in the rd field since the dest registers are hi and lo mfhi and mflo have nothing important in Garcia is Spring 2008 UC CS61C L12 MIPS Instruction Representation I 14 the rs and rt fields since the source R Format Instructions 5 5 Final field shamt This field contains the amount a shift instruction will shift by Shifting a 32 bit word by more than 31 is useless so this field is only 5 bits so it can represent the numbers 0 31 This field is set to 0 in all but the shift instructions
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