inst eecs berkeley edu cs61c Review UC Berkeley CS61C Machine Structures MIPS Machine Language Instruction 32 bits representing a single instruction Lecture 17 Instruction Representation III 2008 03 03 TA Matt Johnson inst eecs berkeley edu cs61c tm R opcode I opcode J opcode iPhone games and general SDK rs rs rt rd shamt funct rt immediate target address Branches use PC relative addressing Jumps use absolute addressing Apple is finally releasing an iPhone Software Developer Kit on March 6th That means iPhone games that use both touch and accelerometer input youtube com watch v hy0ptZisr70 CS61C L17 MIPS Instruction Format III 1 Spring 2008 UCB CS61C L17 MIPS Instruction Format III 2 Outline Decoding Machine Language Disassembly Pseudoinstructions True Assembly Language TAL vs MIPS Assembly Language MAL CS61C L17 MIPS Instruction Format III 3 Spring 2008 UCB Spring 2008 UCB How do we convert 1s and 0s to assembly language and to C code Machine language assembly C For each 32 bits 1 Look at opcode to distinquish between RFormat J Format and I Format 2 Use instruction format to determine which fields exist 3 Write out MIPS assembly code converting each field to name register number name or decimal hex number 4 Logically convert this MIPS code into valid C code Always possible Unique CS61C L17 MIPS Instruction Format III 4 Spring 2008 UCB Decoding Example 1 7 Decoding Example 2 7 Here are six machine language instructions in hexadecimal The six machine language instructions in binary 00000000000000000001000000100101 00000000000001010100000000101010 00010001000000000000000000000011 00000000010001000001000000100000 00100000101001011111111111111111 00001000000100000000000000000001 00001025hex 0005402Ahex 11000003hex 00441020hex 20A5FFFFhex 08100001hex Next step identify opcode and format Let the first instruction be at address 4 194 304ten 0x00400000hex Next step convert hex to binary CS61C L17 MIPS Instruction Format III 5 Spring 2008 UCB R 0 I 1 4 62 J 2 or 3 rs rs CS61C L17 MIPS Instruction Format III 6 rt rd shamt funct rt immediate target address Spring 2008 UCB Decoding Example 3 7 Decoding Example 4 7 Select the opcode first 6 bits to determine the format Fields separated based on format opcode Format R R I R I J Format 00000000000000000001000000100101 00000000000001010100000000101010 00010001000000000000000000000011 00000000010001000001000000100000 00100000101001011111111111111111 00001000000100000000000000000001 R R I R I J Look at opcode 0 means R Format 2 or 3 mean J Format otherwise I Format 0 0 8 2 5 0 5 0 4 5 2 8 2 Spring 2008 UCB 37 42 32 1 048 577 CS61C L17 MIPS Instruction Format III 8 Spring 2008 UCB Decoding Example 5 7 Decoding Example 6 7 MIPS Assembly Part 1 MIPS Assembly Part 2 Address 0 0 3 0 1 Next step translate disassemble to MIPS assembly instructions Next step separation of fields CS61C L17 MIPS Instruction Format III 7 0 0 4 0 8 2 Assembly instructions 0x00400000 0x00400004 0x00400008 0x0040000c 0x00400010 0x00400014 or slt beq add addi j 2 0 0 8 0 5 8 0 3 2 2 4 5 5 1 0x100001 Loop Better solution translate to more meaningful MIPS instructions fix the branch jump and add labels registers CS61C L17 MIPS Instruction Format III 9 Spring 2008 UCB Decoding Example 7 7 After C code Mapping below Exit or slt beq add addi j v0 0 0 t0 0 a1 t0 0 Exit v0 v0 a0 a1 a1 1 Loop Next step translate to C code must be creative CS61C L17 MIPS Instruction Format III 10 Spring 2008 UCB Administrivia Before Hex 00001025hex 0005402Ahex 11000003hex 00441020hex 20A5FFFFhex 08100001hex or Loop slt beq add addi j Exit v0 product a0 multiplicand a1 multiplier product 0 while multiplier 0 product multiplicand multiplier 1 v0 0 0 t0 0 a1 t0 0 Exit v0 v0 a0 a1 a1 1 Loop CS61C L17 MIPS Instruction Format III 11 Demonstrated Big 61C Idea Instructions are just numbers code is treated like data Spring 2008 UCB Midterm is next week Day and location are still TBA Old midterms online link at top of page Lectures and reading materials fair game Fix green sheet errors if old book Review session also TBA Project 2 is due March 5 at 11 59PM That s Wednesday There was a file update See spec page CS61C L17 MIPS Instruction Format III 12 Spring 2008 UCB Review from before lui So how does lui help us True Assembly Language 1 3 Pseudoinstruction A MIPS instruction that doesn t turn directly into a machine language instruction but into other MIPS instructions Example addi becomes lui ori add t0 t0 0xABABCDCD What happens with pseudo instructions at 0xABAB at at 0xCDCD t0 t0 at Now each I format instruction has only a 16bit immediate They re broken up by the assembler into several real MIPS instructions Some examples follow Wouldn t it be nice if the assembler would this for us automatically If number too big then just automatically replace addi with lui ori add CS61C L17 MIPS Instruction Format III 13 Spring 2008 UCB Example Pseudoinstructions Load Address How do we get the address of an instruction or global variable into a register move reg2 reg1 Expands to add reg2 zero reg1 Load Immediate li reg value If value fits in 16 bits addi reg zero value else lui reg upper 16 bits of value ori reg zero lower 16 bits Spring 2008 UCB la reg label Again if value fits in 16 bits addi reg zero label value else lui reg upper 16 bits of value ori reg zero lower 16 bits CS61C L17 MIPS Instruction Format III 16 Spring 2008 UCB Example Pseudoinstructions True Assembly Language 2 3 Problem Rotate Right Instruction When breaking up a pseudo instruction the assembler may need to use an extra register If it uses any regular register it ll overwrite whatever the program has put into it Solution Reserve a register 1 called at for assembler temporary that assembler will use to break up pseudo instructions Since the assembler may use this at any time it s not safe to code with it CS61C L17 MIPS Instruction Format III 17 Spring 2008 UCB Example Pseudoinstructions Register Move CS61C L17 MIPS Instruction Format III 15 CS61C L17 MIPS Instruction Format III 14 Spring 2008 UCB ror reg Expands to srl at sll reg or reg value reg value reg 32 value reg at 0 0 No OPeration instruction nop Expands to instruction 0ten sll 0 0 0 CS61C L17 MIPS Instruction Format III 18 Spring 2008 UCB Example Pseudoinstructions True Assembly Language 3 3 Wrong operation for operand addu reg reg value should be addiu If value fits in 16 bits addu is changed to addiu reg reg value else lui at upper 16 bits of value ori at at lower 16 bits addu reg reg at
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