CS61C Input/Output Lecture 12“Review..” 1/1OutlineAnatomy: 5 components of any ComputerMotivation for Input/OutputI/O Device Examples and SpeedsInstruction Set Architecture for I/OProcessor-I/O Speed MismatchProcessor Checks Status before ActingSPIM I/O SimulationSPIM I/OI/O ExampleAdministrivia“Computers in the News”Cost of Polling?% Processor time to poll mouse, floppy% Processor time to hard diskWhat is the alternative to polling?I/O InterruptInterrupt Driven Data TransferInstruction Set support for I/O InterruptSlide 22SPIM I/O Simulation: Interrupt Driven I/OExample Interrupt RoutineBenefit of Interrupt-Driven I/OQuestions Raised about Interrupts4 Responsibilities leading to OS4 Functions OS must providecs 61C L12 I/O.1Patterson Spring 99 ©UCBCS61CInput/Output Lecture 12February 26, 1999Dave Patterson (http.cs.berkeley.edu/~patterson)www-inst.eecs.berkeley.edu/~cs61c/schedule.htmlcs 61C L12 I/O.2Patterson Spring 99 ©UCB“Review..” 1/1°Pointer is high level language version of address•Powerful yet dangerous concept°Like goto, with self-imposed discipline can achieve clarity and simplicity•Also can cause difficult to fix bugs°C supports pointers, pointer arithmetic°Java structure pointers have many of the same potential problems!cs 61C L12 I/O.3Patterson Spring 99 ©UCBOutline°Input/Output (I/O) Motivation and Speed°Instruction set support for I/O°Synchronizing Processor and I/O devices°Polling to synchronize°Administrivia, “Computers in the News”°Example I/O interface: SPIM°Weaknesses of Polling°Interrupts to synchronize°Conclusioncs 61C L12 I/O.4Patterson Spring 99 ©UCBAnatomy: 5 components of any Computer Processor (active)ComputerControl(“brain”)Datapath(“brawn”)Memory(passive)(where programs, data live whenrunning)DevicesInputOutputKeyboard, MouseDisplay, PrinterDisk (where programs, data live when not running)Lectures 1-11 Lectures 12-14cs 61C L12 I/O.5Patterson Spring 99 ©UCBMotivation for Input/Output°I/O is how humans interact with computers°I/O lets computers do amazing things:•Read pressure of synthetic hand and control synthetic arm and hand of fireman•Control propellers, fins, communicate in BOB (Breathable Observable Bubble)•Read bar codes of items in refrigerator°Computer without I/O like a car without wheels; great technology, but won’t get you anywherecs 61C L12 I/O.6Patterson Spring 99 ©UCBI/O Device Examples and Speeds°I/O Speed: bytes transferred per second(from mouse to display: million-to-1) °Device Behavior Partner Data Rate (Kbytes/sec)Keyboard Input Human 0.01Mouse Input Human 0.02Line Printer Output Human 1.00Floppy disk Storage Machine 50.00Laser Printer Output Human 100.00Optical Disk Storage Machine 500.00Magnetic Disk Storage Machine 10,000.00Network-LAN I or O Machine 10,000.00Graphics Display Output Human 30,000.00cs 61C L12 I/O.7Patterson Spring 99 ©UCBInstruction Set Architecture for I/O°Some machines have special input and output instructions°Alternative model (used by MIPS):•Input: ~ reads a sequence of bytes •Output: ~ writes a sequence of bytes°Memory also a sequence of bytes, so use loads for input, stores for output•Called “Memory Mapped Input/Output”•A portion of the address space dedicated to communication paths to Input or Output devices (no memory there)cs 61C L12 I/O.8Patterson Spring 99 ©UCBProcessor-I/O Speed Mismatch°500 MHz microprocessor can execute a 500 million load or store instructions per second, or 200,000 KB/s data rate•I/O devices from 0.01 KB/s to 30,000 KB/s°Input: device may not be ready to send data as fast as the processor loads it•Also, might be waiting for human to act°Output: device may not be ready to accept data as fast as processor stores it°What to do?cs 61C L12 I/O.9Patterson Spring 99 ©UCBProcessor Checks Status before Acting°Path to device generally has 2 registers:•1 register says its OK to read/write (I/O ready), often called Control Register•1 register to contain data, often called Data Register°Processor reads from Control Register in loop, waiting for device to set Ready bit in Control reg to say its OK (0 1)°Processor then loads from (input) or writes to (output) data register•Load from device/Store into Data Register resets Ready bit (1 0) of Control Registercs 61C L12 I/O.10Patterson Spring 99 ©UCBSPIM I/O Simulation°SPIM simulates 1 I/O device: memory-mapped terminal (keyboard + display)•Read from keyboard (receiver); 2 device regs•Writes to terminal (transmitter); 2 device regsReceived ByteReceiver Data0xffff0004Unused (00...00)(IE)Receiver Control0xffff0000Ready(I.E.)Unused (00...00)TransmittedByteTransmitter Control0xffff0008Transmitter Data0xffff000cReady(I.E.)Unused (00...00)Unusedcs 61C L12 I/O.11Patterson Spring 99 ©UCBSPIM I/O°Control register rightmost bit (0): Ready•It cannot be changed by processor (like $0)•Receiver: Ready==1 means character in Data Register not yet been read; 1 0 when data is read from Data Reg•Transmitter: Ready==1 means transmitter is ready to accept a new character;0 Transmitter still busy writing last char-(I.E. discussed later)°Data register rightmost byte has data•Receiver: last char from keyboard; rest = 0•Transmitter: when write rightmost byte, writes char to displaycs 61C L12 I/O.12Patterson Spring 99 ©UCBI/O Example°Input: Read from keyboard into $v0lui $t0, 0xffff # ffff0000Waitloop: lw $t1, 0($t0) # controlandi $t1,$t1,0x0001beq $t1,$zero, Waitlooplw $v0, 4($t0) # data°Output: Write to display from $a0lui $t0, 0xffff # ffff0000Waitloop: lw $t1, 8($t0) # controlandi $t1,$t1,0x0001beq $t1,$zero, Waitloopsw $a0, 12($t0) # data°Processor waiting for I/O called “Polling”cs 61C L12 I/O.13Patterson Spring 99 ©UCBAdministrivia°Readings: Pointers: COD: 3.11, K&R Ch. 5; I/O 8.3, 8.5, A.7, A.8°6th homework: Due 3/3 7PM•Exercises 8.1, 8.5, 8.8°3rd Project/5th Lab: MIPS Simulator Due Wed. 3/3 7PM; deadline Thurs 8AM°Upcoming events•Midterm on 3/17 5pm-8PM, 1 Pimentel•4th Project due same day as midterm???4th Project due Wed. 3/10•2nd online questionnaire when demo 6th labcs 61C L12 I/O.14Patterson Spring 99 ©UCB“Computers in the News”°“Intel Demonstrates Performance of New Pentium Microprocessor”, NY Times, 2/24/99• Intel has tried to position the Pentium III as a “next generation”microprocessor, but industry analysts have generally viewed
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