CS 61C L17 Control (1)A Carle, Summer 2005 © UCBinst.eecs.berkeley.edu/~cs61c/su05CS61C : Machine StructuresLecture #17: CPU Design II – Control2005-07-19Andy CarleCS 61C L17 Control (2)A Carle, Summer 2005 © UCBAnatomy: 5 components of any ComputerPersonal ComputerProcessorComputerControl(“brain”)Datapath(“brawn”)Memory(where programs, data live whenrunning)DevicesInputOutputKeyboard, MouseDisplay, PrinterDisk(where programs, data live whennot running)This weekCS 61C L17 Control (3)A Carle, Summer 2005 © UCBReview: A Single Cycle Datapath•Rs, Rt, Rd, Imed16 connected to datapath•We have everything except control signals32ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMuxMux3216imm16ALUSrcExtOpMuxMemtoRegClkData InWrEn32AdrDataMemory32MemWrALUInstructionFetch UnitClkZeroInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRtnPC_selCS 61C L17 Control (4)A Carle, Summer 2005 © UCBAn Abstract View of the Critical PathCritical Path (Load Operation) = Delay clock through PC (FFs) +Instruction Memory’s Access Time +Register File’s Access Time, +ALU to Perform a 32-bit Add +Data Memory Access Time +Stable Time for Register File WriteClk5Rw Ra Rb32 32-bitRegistersRdALUClkData InDataAddressIdealDataMemoryInstructionInstructionAddressIdealInstructionMemoryClkPC5Rs5Rt16Imm32323232ABNext Address• This affects how much you can overclockyour PC!CS 61C L17 Control (5)A Carle, Summer 2005 © UCBRecap: Meaning of the Control Signals•nPC_MUX_sel: 0 ⇒ PC <– PC + 4 1 ⇒ PC <– PC + 4 + {SignExt(Im16) , 00 }•Later in lecture: higher-level connection between mux and branch condAdrInstMemoryAdderAdderPCClk00Mux4nPC_MUX_selPC Extimm16“n”=nextCS 61C L17 Control (6)A Carle, Summer 2005 © UCBRecap: Meaning of the Control Signals• ExtOp: “zero”, “sign”• ALUsrc: 0 ⇒ regB; 1 ⇒ immed• ALUctr: “add”, “sub”, “or”° MemWr: 1 ⇒ write memory° MemtoReg: 0 ⇒ ALU; 1 ⇒ Mem° RegDst: 0 ⇒ “rt”; 1 ⇒ “rd”° RegWr: 1 ⇒ write register32ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMux3216imm16ALUSrcExtOpMuxMemtoRegClkData InWrEn32AdrDataMemoryMemWrALUEqual010101=CS 61C L17 Control (7)A Carle, Summer 2005 © UCBRTL: The Add Instructionadd rd, rs, rt•MEM[PC] Fetch the instruction from memory•R[rd] = R[rs] + R[rt] The actual operation•PC = PC + 4 Calculate the next instruction’s addressop rs rt rd shamt funct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsCS 61C L17 Control (8)A Carle, Summer 2005 © UCBInstruction Fetch Unit at the Beginning of Add•Fetch the instruction from Instruction memory: Instruction = MEM[PC]• same for all instructionsPC ExtAdrInstMemoryAdderAdderPCClk00Mux4nPC_MUX_selimm16Instruction<31:0>CS 61C L17 Control (9)A Carle, Summer 2005 © UCBThe Single Cycle Datapath during Add32ALUctr = AddClkbusWRegWr = 13232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = 1ExtenderMuxMux3216imm16ALUSrc = 0ExtOp = xMuxMemtoReg = 0ClkData InWrEn32AdrDataMemory32MemWr = 0ALUInstructionFetch UnitClkZeroInstruction<31:0>•R[rd] = R[rs] + R[rt]010101<21:25><16:20><11:15><0:15>Imm16RdRsRtop rs rt rd shamt funct061116212631nPC_sel= +4CS 61C L17 Control (10)A Carle, Summer 2005 © UCBInstruction Fetch Unit at the End of Add•PC = PC + 4• This is the same for all instructions except: Branch and JumpAdrInstMemoryAdderAdderPCClk00Mux4nPC_MUX_selimm16Instruction<31:0>01CS 61C L17 Control (11)A Carle, Summer 2005 © UCBSingle Cycle Datapath during Or Immediate?op rs rt immediate01621263132ALUctr = ClkbusWRegWr = 3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = ExtenderMuxMux3216imm16ALUSrc = ExtOp = MuxMemtoReg = ClkData InWrEn32AdrDataMemory32MemWr = ALUInstructionFetch UnitClkZeroInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRtnPC_sel = •R[rt] = R[rs] OR ZeroExt[Imm16]CS 61C L17 Control (12)A Carle, Summer 2005 © UCB32ALUctr = OrClkbusWRegWr = 13232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = 0ExtenderMuxMux3216imm16ALUSrc = 1ExtOp = 0MuxMemtoReg = 0ClkData InWrEn32AdrDataMemory32MemWr = 0ALUInstructionFetch UnitClkZeroInstruction<31:0>•R[rt] = R[rs] OR ZeroExt[Imm16]010101<21:25><16:20><11:15><0:15>Imm16RdRsRtop rs rt immediate016212631nPC_sel= +4Single Cycle Datapath during Or Immediate?CS 61C L17 Control (13)A Carle, Summer 2005 © UCBThe Single Cycle Datapath during Load?32ALUctr=ClkbusWRegWr =3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst =ExtenderMuxMux3216imm16ALUSrc =ExtOp =MuxMemtoReg =ClkData InWrEn32AdrDataMemory32MemWr =ALUInstructionFetch UnitClkZeroInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRt• R[rt] = Data Memory {R[rs] + SignExt[imm16]}op rs rt immediate016212631nPC_sel=CS 61C L17 Control (14)A Carle, Summer 2005 © UCBThe Single Cycle Datapath during Load32ALUctr= AddClkbusWRegWr = 13232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = 0ExtenderMuxMux3216imm16ALUSrc = 1ExtOp = 1MuxMemtoReg = 1ClkData InWrEn32AdrDataMemory32MemWr = 0ALUInstructionFetch UnitClkZeroInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRt• R[rt] = Data Memory {R[rs] + SignExt[imm16]}op rs rt immediate016212631nPC_sel= +4CS 61C L17 Control (15)A Carle, Summer 2005 © UCBThe Single Cycle Datapath during Store?op rs rt immediate01621263132ALUctr = ClkbusWRegWr = 3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = ExtenderMuxMux3216imm16ALUSrc = ExtOp = MuxMemtoReg = ClkData InWrEn32AdrDataMemory32MemWr = ALUInstructionFetch UnitClkZeroInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRtnPC_sel = • Data Memory {R[rs] + SignExt[imm16]} = R[rt]CS 61C L17 Control (16)A Carle, Summer 2005 © UCBThe Single Cycle Datapath during Store32ALUctr= AddClkbusWRegWr = 03232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = xExtenderMuxMux3216imm16ALUSrc = 1ExtOp = 1MuxMemtoReg = xClkData InWrEn32AdrDataMemory32MemWr = 1ALUInstructionFetch UnitClkZeroInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRt• Data Memory {R[rs] + SignExt[imm16]} = R[rt]op rs rt immediate016212631nPC_sel= +4CS 61C L17 Control (17)A Carle, Summer 2005 © UCBThe Single Cycle Datapath during Branch?32ALUctr =ClkbusWRegWr =3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst =ExtenderMuxMux3216imm16ALUSrc =ExtOp =MuxMemtoReg = xClkData InWrEn32AdrDataMemory32MemWr =ALUInstructionFetch
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