inst eecs berkeley edu cs61c su05 CS61C Machine Structures Lecture 17 CPU Design II Control Anatomy 5 components of any Computer Personal Computer Keyboard Mouse Computer Processor Control brain This week Datapath brawn Memory Devices Disk Input where programs data live when running where programs data live when not running Output Display Printer 2005 07 19 Andy Carle Review A Single Cycle Datapath Rs Rt Rd Imed16 connected to datapath We have everything except control signals Instruction 31 0 Memory Next Address 1 Rd Rs Rt 5 5 5 Instruction Address 32 Clk WrEn Adr Data Memory Critical Path Load Operation Delay clock through PC FFs This affects how much you Instruction Memory s Access Time can overclock Register File s Access Time your PC ALU to Perform a 32 bit Add Data Memory Access Time Ideal Stable Time for Register File Write Instruction Instruction Imm 16 A Rw Ra Rb 32 32 bit 32 Registers B Clk Data 32 Address ALU Clk ALUSrc 0 32 An Abstract View of the Critical Path MemtoReg Mux 32 Data In32 0 15 1 Rs Rd Imm16 MemWr 32 Mux 16 Extender imm16 ALU busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 busW 32 Clk Rt Zero ALUctr 11 15 Clk 16 20 Rd Rt 1 Mux0 Rs Rt RegWr 5 5 5 RegDst Instruction Fetch Unit 21 25 nPC sel A Carle Summer 2005 UCB CS 61C L17 Control 2 PC A Carle Summer 2005 UCB CS 61C L17 Control 1 Data In Ideal Data Memory Clk 32 ExtOp A Carle Summer 2005 UCB CS 61C L17 Control 3 Recap Meaning of the Control Signals 0 PC PC 4 1 PC PC 4 SignExt Im16 00 Later in lecture higher level connection between mux and branch cond nPC MUX sel n next nPC MUX sel Inst Adr Memory 00 Clk A Carle Summer 2005 UCB CS 61C L17 Control 6 ALUctr MemWr MemtoReg 32 32 WrEnAdr Data In Data Memory Clk ExtOp ALUSrc 0 Mux Equal Rd Rt 1 0 Rs Rt RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32 bit 32 Registers busB 0 32 Clk 1 imm16 32 16 Mux Adder imm16 RegDst Extender PC Mux Adder PC Ext CS 61C L17 Control 5 Recap Meaning of the Control Signals MemWr 1 write memory ExtOp zero sign MemtoReg 0 ALU 1 Mem ALUsrc 0 regB 1 immed RegDst 0 rt 1 rd ALUctr add sub or RegWr 1 write register ALU 4 A Carle Summer 2005 UCB CS 61C L17 Control 4 1 A Carle Summer 2005 UCB RTL The Add Instruction 21 op 16 rs 6 bits 11 rt 5 bits 5 bits 6 Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory Instruction MEM PC 0 rd shamt funct 5 bits 5 bits 6 bits same for all instructions add rd rs rt MEM PC Fetch the instruction from memory R rd R rs R rt The actual operation PC PC 4 Calculate the next instruction s address 4 imm16 21 16 rs 11 rt 6 rd R rd R rs R rt 1 Mux 0 Rs 5 5 ALUctr Add Rt Rt 32 Imm16 nPC MUX sel 32 Clk ExtOp x A Carle Summer 2005 UCB CS 61C L17 Control 9 Single Cycle Datapath during Or Immediate 26 op 21 rs 16 Clk A Carle Summer 2005 UCB Single Cycle Datapath during Or Immediate 31 26 immediate op R rt R rs OR ZeroExt Imm16 1 CS 61C L17 Control 10 0 rt 0 Adder 32 Data Memory PC Data In 32 Mux 1 WrEn Adr 1 4 0 32 Mux 0 ALUSrc 0 31 Instruction 31 0 MemWr 0 Adder ALU 16 Zero Mux Extender imm16 Inst Memory Adr MemtoReg 0 Rw Ra Rb 32 32 bit Registers busB 32 32 Clk Rd 5 busA busW Rs Instruction Fetch Unit at the End of Add PC PC 4 imm16 RegWr 1 A Carle Summer 2005 UCB CS 61C L17 Control 8 0 15 Clk 11 15 Rt Instruction Fetch Unit Clk This is the same for all instructions except Branch and Jump Instruction 31 0 16 20 Rd RegDst 1 funct 21 25 nPC sel 4 0 shamt PC 26 op Adder 31 Mux Adder The Single Cycle Datapath during Add Instruction 31 0 nPC MUX sel PC Ext A Carle Summer 2005 UCB CS 61C L17 Control 7 Inst Memory Adr 00 26 00 31 21 16 rs 0 rt immediate R rt R rs OR ZeroExt Imm16 Instruction 31 0 16 ALUSrc Imm16 MemtoReg 0 MemWr 0 0 32 WrEn Adr Data In 32 Clk 32 1 Data Memory ALUSrc 1 ExtOp CS 61C L17 Control 11 1 32 Rs Rd Mux imm16 0 15 Clk Rw Ra Rb 32 32 32 bit Registers busB 0 32 1 Data Memory Zero ALU WrEn Adr Data In 32 Rt ALUctr Or Mux 1 32 32 32 Clk Extender 16 Extender imm16 busW 0 32 Rs Rt 5 5 busA Mux Rw Ra Rb 32 32 32 bit Registers busB 0 32 Mux 32 Clk Clk 1 Mux 0 RegWr 15 Zero MemWr ALU busW Rt Rd RegDst 0 11 15 busA Imm16 MemtoReg Instruction Fetch Unit 16 20 ALUctr Rs Rd nPC sel 4 21 25 5 Rt Instruction 31 0 0 15 RegWr Rs Rt 5 5 11 15 Clk 1 Mux 0 16 20 Rt Rd RegDst Instruction Fetch Unit 21 25 nPC sel ExtOp 0 A Carle Summer 2005 UCB CS 61C L17 Control 12 A Carle Summer 2005 UCB The Single Cycle Datapath during Load 31 26 21 op 16 rs The Single Cycle Datapath during Load 0 rt 31 26 immediate 21 op R rt Data Memory R rs SignExt imm16 16 rs 0 rt immediate R rt Data Memory R rs SignExt imm16 Instruction 31 0 5 busA ALUctr Add 5 imm16 16 ExtOp 26 21 16 rs Data In 32 Data Memory Clk A Carle Summer 2005 UCB 31 26 op 21 16 rs 0 rt immediate Data Memory R rs SignExt imm16 R rt The Single Cycle Datapath during Branch 21 16 31 0 32 WrEn Adr Data In 32 Clk 32 1 Data Memory ALUSrc 0 ExtOp CS 61C L17 Control 17 Imm16 MemtoReg x Mux 16 ALUSrc 1 32 0 15 imm16 Rs Rd Zero MemWr 0 Rw Ra Rb 32 32 32 bit Registers busB 0 32 1 Data Memory 11 15 32 Clk 16 20 Clk 5 Rt ALUctr Sub Rs Rt 5 5 ALU WrEn Adr Data In 32 Clk 1 Mux 0 RegWr 0 Instruction Fetch Unit Mux 1 32 Rt Rd RegDst x Extender 16 Extender imm16 32 Instruction 31 0 nPC sel Br busW 0 32 0 immediate busA Mux Rw Ra Rb 32 32 32 bit Registers busB 0 32 Mux 32 Clk 16 rt if R rs R rt 0 then Zero 1 else Zero 0 Zero MemWr ALU busW Imm16 MemtoReg x 21 rs 21 25 busA Rs Rd 0 15 5 Rt ALUctr 11 15 Clk Rs Rt 5 5 26 op …
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